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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-04 20:46:31 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-04 20:46:31 +0000 |
| commit | 2df41a8e38976de5a161b2cd06bc5d1e0136df74 (patch) | |
| tree | 9f1ca8fb2320e433ec01c5adeb96cdc5e5ce031c /llvm/lib/Target | |
| parent | 5ff310e298058cf13cace70839b0ca8cc26fc262 (diff) | |
| download | bcm5719-llvm-2df41a8e38976de5a161b2cd06bc5d1e0136df74.tar.gz bcm5719-llvm-2df41a8e38976de5a161b2cd06bc5d1e0136df74.zip | |
AMDGPU/GlobalISel: Select G_BITREVERSE
llvm-svn: 370980
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP1Instructions.td | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index d0382bf3772..bffc3dd3295 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -1775,6 +1775,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case AMDGPU::G_CTTZ_ZERO_UNDEF: case AMDGPU::G_CTPOP: case AMDGPU::G_BSWAP: + case AMDGPU::G_BITREVERSE: case AMDGPU::G_FABS: case AMDGPU::G_FNEG: { unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td index 6bc416ed7d4..e5890cb2cb8 100644 --- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -227,7 +227,7 @@ defm V_COS_F32 : VOP1Inst <"v_cos_f32", VOP_F32_F32, AMDGPUcos>; } // End SchedRW = [WriteQuarterRate32] defm V_NOT_B32 : VOP1Inst <"v_not_b32", VOP_I32_I32>; -defm V_BFREV_B32 : VOP1Inst <"v_bfrev_b32", VOP_I32_I32>; +defm V_BFREV_B32 : VOP1Inst <"v_bfrev_b32", VOP_I32_I32, bitreverse>; defm V_FFBH_U32 : VOP1Inst <"v_ffbh_u32", VOP_I32_I32>; defm V_FFBL_B32 : VOP1Inst <"v_ffbl_b32", VOP_I32_I32>; defm V_FFBH_I32 : VOP1Inst <"v_ffbh_i32", VOP_I32_I32>; |
