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author | Craig Topper <craig.topper@intel.com> | 2018-07-05 03:01:29 +0000 |
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committer | Craig Topper <craig.topper@intel.com> | 2018-07-05 03:01:29 +0000 |
commit | 2db909cfae13f8cab5b02bce5490760e01da96e9 (patch) | |
tree | e0f0f495418008fc63666c10047b0ee3327c495a /llvm/lib/Target | |
parent | 95eb88abfe17c1b1faeb5252554117d45cb2f50e (diff) | |
download | bcm5719-llvm-2db909cfae13f8cab5b02bce5490760e01da96e9.tar.gz bcm5719-llvm-2db909cfae13f8cab5b02bce5490760e01da96e9.zip |
[X86] Remove some isel patterns for X86ISD::SELECTS that specifically looked for the v1i1 mask to have come from a scalar_to_vector from GR8.
We have patterns for SELECTS that top at v1i1 and we have a pattern for (v1i1 (scalar_to_vector GR8)). The patterns being removed here do the same thing as the two other patterns combined so there is no need for them.
llvm-svn: 336305
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index b93b095af0f..be7889e4912 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -4248,29 +4248,11 @@ defm : avx512_load_scalar_lowering_subreg2<"VMOVSDZ", avx512vl_f64_info, (v8i1 (bitconvert (i8 (and GR8:$mask, (i8 1))))), (iPTR 0))), GR8, sub_8bit>; -def : Pat<(f32 (X86selects (scalar_to_vector GR8:$mask), - (f32 FR32X:$src1), (f32 FR32X:$src2))), - (COPY_TO_REGCLASS - (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X), - (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), - GR8:$mask, sub_8bit)), VK1WM), - (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src1, VR128X)), - FR32X)>; - def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))), (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X), VK1WM:$mask, (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src1, VR128X)), FR32X)>; -def : Pat<(f64 (X86selects (scalar_to_vector GR8:$mask), - (f64 FR64X:$src1), (f64 FR64X:$src2))), - (COPY_TO_REGCLASS - (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X), - (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), - GR8:$mask, sub_8bit)), VK1WM), - (v2f64 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR64X:$src1, VR128X)), - FR64X)>; - def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))), (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X), VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), |