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| author | David Majnemer <david.majnemer@gmail.com> | 2016-08-12 04:32:42 +0000 |
|---|---|---|
| committer | David Majnemer <david.majnemer@gmail.com> | 2016-08-12 04:32:42 +0000 |
| commit | 2d006e767341a2f9ea57a9cb5cea055849a8c684 (patch) | |
| tree | 241cd093f21977c1a053ffc326d6619526159c4a /llvm/lib/Target | |
| parent | c700490f485f78e1d6d1b6577d17ef76066bcf1f (diff) | |
| download | bcm5719-llvm-2d006e767341a2f9ea57a9cb5cea055849a8c684.tar.gz bcm5719-llvm-2d006e767341a2f9ea57a9cb5cea055849a8c684.zip | |
Use the range variant of transform instead of unpacking begin/end
No functionality change is intended.
llvm-svn: 278476
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 8d649250f65..383b7ca4ddd 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -1266,7 +1266,7 @@ void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs, SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); if (Narrow) - std::transform(Regs.begin(), Regs.end(), Regs.begin(), + transform(Regs, Regs.begin(), WidenVector(*CurDAG)); SDValue RegSeq = createQTuple(Regs); @@ -1305,7 +1305,7 @@ void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs, SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); if (Narrow) - std::transform(Regs.begin(), Regs.end(), Regs.begin(), + transform(Regs, Regs.begin(), WidenVector(*CurDAG)); SDValue RegSeq = createQTuple(Regs); @@ -1360,7 +1360,7 @@ void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs, SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); if (Narrow) - std::transform(Regs.begin(), Regs.end(), Regs.begin(), + transform(Regs, Regs.begin(), WidenVector(*CurDAG)); SDValue RegSeq = createQTuple(Regs); @@ -1390,7 +1390,7 @@ void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs, SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); if (Narrow) - std::transform(Regs.begin(), Regs.end(), Regs.begin(), + transform(Regs, Regs.begin(), WidenVector(*CurDAG)); SDValue RegSeq = createQTuple(Regs); |
