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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-21 23:23:16 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-21 23:23:16 +0000 |
| commit | 2cba91b8dbf408d4e81195e821939e9409746f25 (patch) | |
| tree | dddcc60383cfe287f89c4cf0fc004df29608a1ab /llvm/lib/Target | |
| parent | eea81c20fef4f5bdcbe4d0a240591c10d313fa1b (diff) | |
| download | bcm5719-llvm-2cba91b8dbf408d4e81195e821939e9409746f25.tar.gz bcm5719-llvm-2cba91b8dbf408d4e81195e821939e9409746f25.zip | |
AMDGPU: Assume calls read exec
llvm-svn: 361333
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index dd7f173e44d..e781253dd01 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2514,6 +2514,10 @@ bool SIInstrInfo::mayReadEXEC(const MachineRegisterInfo &MRI, return MI.readsRegister(AMDGPU::EXEC, &RI); } + // Make a conservative assumption about the callee. + if (MI.isCall()) + return true; + // Be conservative with any unhandled generic opcodes. if (!isTargetSpecificOpcode(MI.getOpcode())) return true; |
