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| author | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-05-22 04:46:46 +0000 |
|---|---|---|
| committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-05-22 04:46:46 +0000 |
| commit | 2bd1262a3299ca9c9ac936df6d17f52858d21ef8 (patch) | |
| tree | 29f9186fa37c0f97ea47a4cf112db958e3d3444f /llvm/lib/Target | |
| parent | 49a2790fb329c5cf27d9735b97ef70a6760921e4 (diff) | |
| download | bcm5719-llvm-2bd1262a3299ca9c9ac936df6d17f52858d21ef8.tar.gz bcm5719-llvm-2bd1262a3299ca9c9ac936df6d17f52858d21ef8.zip | |
ARM: introduce llvm.arm.undefined intrinsic
This intrinsic permits the emission of platform specific undefined sequences.
ARM has reserved the 0xde opcode which takes a single integer parameter (ignored
by the CPU). This permits the operating system to implement custom behaviour on
this trap. The llvm.arm.undefined intrinsic is meant to provide a means for
generating the target specific behaviour from the frontend. This is
particularly useful for Windows on ARM which has made use of a series of these
special opcodes.
llvm-svn: 209390
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index f642893161c..718d5da9d05 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -1969,7 +1969,7 @@ def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", // A8.8.247 UDF - Undefined (Encoding A1) def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, - "udf", "\t$imm16", []> { + "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { bits<16> imm16; let Inst{31-28} = 0b1110; // AL let Inst{27-25} = 0b011; diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index ff3832d98b5..e17f73af03e 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -1194,8 +1194,8 @@ def tTST : // A8.6.230 Sched<[WriteALU]>; // A8.8.247 UDF - Undefined (Encoding T1) -def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", []>, - Encoding16 { +def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", + [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 { bits<8> imm8; let Inst{15-12} = 0b1101; let Inst{11-8} = 0b1110; diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 28f528a510e..c30d6abbb29 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -2408,8 +2408,8 @@ def t2UBFX: T2TwoRegBitFI< } // A8.8.247 UDF - Undefined (Encoding T2) -def t2UDF - : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16", []> { +def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16", + [(int_arm_undefined imm0_65535:$imm16)]> { bits<16> imm16; let Inst{31-29} = 0b111; let Inst{28-27} = 0b10; |
