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authorChris Lattner <sabre@nondot.org>2007-11-04 06:51:12 +0000
committerChris Lattner <sabre@nondot.org>2007-11-04 06:51:12 +0000
commit296160d4434b13d4d828dba535c81dea1712632f (patch)
treec77dc431f418d61cd8609e1f96810506bc082570 /llvm/lib/Target
parentce8c62665ae132494130a0c580099b879a6457fd (diff)
downloadbcm5719-llvm-296160d4434b13d4d828dba535c81dea1712632f.tar.gz
bcm5719-llvm-296160d4434b13d4d828dba535c81dea1712632f.zip
Fix PR1763 by allowing the 'q' constraint to work with 64-bit
regs on x86-64. llvm-svn: 43669
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index dc9cf99fde6..58004f0201e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -5708,7 +5708,9 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
else if (VT == MVT::i8)
return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
- break;
+ else if (VT == MVT::i64)
+ return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
+ break;
}
}
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