Add doubleword load/store (64-bit only).

llvm-svn: 15665

2 files changed, 29 insertions, 5 deletions

diff --git a/llvm/lib/Target/PowerPC/PowerPCInstrFormats.td b/llvm/lib/Target/PowerPC/PowerPCInstrFormats.td
index a5b5aaeaee0..852e43255a3 100644
--- a/llvm/lib/Target/PowerPC/PowerPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PowerPCInstrFormats.td
@@ -222,13 +222,35 @@ class DForm_9<string name, bits<6> opcode, bit ppc64, bit vmx>
   let Arg0Type = Fpr.Value;
 }
 
+// 1.7.5 DS-Form
+class DSForm_1<string name, bits<6> opcode, bits<2> xo, bit ppc64, bit vmx> 
+  : I<name, opcode, ppc64, vmx> {
+  field bits<5>  RST;
+  field bits<14> DS;
+  field bits<5>  RA;
+
+  let ArgCount = 3;
+  let Arg0Type = Gpr.Value;
+  let Arg1Type = Disimm14.Value;
+  let Arg2Type = Gpr.Value;
+  let Arg3Type = 0;
+  let Arg4Type = 0;
+
+  let Inst{6-10}  = RST;
+  let Inst{11-15} = RA;
+  let Inst{16-29} = DS;
+  let Inst{30-31} = xo;
+}
+
+class DSForm_2<string name, bits<6> opcode, bits<2> xo, bit ppc64, bit vmx>
+  : DSForm_1<name, opcode, xo, ppc64, vmx>;
+
 // 1.7.6 X-Form
 class XForm_base_r3xo<string name, bits<6> opcode, bits<10> xo, bit rc, 
                       bit ppc64, bit vmx> : I<name, opcode, ppc64, vmx> {
-  let ArgCount = 3;
-  field bits<5>  ST;
-  field bits<5>  A;
-  field bits<5>  B;
+  field bits<5> RST;
+  field bits<5> A;
+  field bits<5> B;
 
   let ArgCount = 3;
   let Arg0Type = Gpr.Value;
@@ -237,7 +259,7 @@ class XForm_base_r3xo<string name, bits<6> opcode, bits<10> xo, bit rc,
   let Arg3Type = 0;
   let Arg4Type = 0;
 
-  let Inst{6-10}  = ST;
+  let Inst{6-10}  = RST;
   let Inst{11-15} = A;
   let Inst{16-20} = B;
   let Inst{21-30} = xo;
diff --git a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
index 0f68911fea4..46f7924ee27 100644
--- a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
@@ -105,6 +105,7 @@ def LHA : DForm_1<"lha", 42, 0, 0>;
 def LHAX : XForm_1<"lhax", 31, 343, 0, 0>;
 def LWZ : DForm_1<"lwz", 32, 0, 0>;
 def LWZX : XForm_1<"lwzx", 31, 23, 0, 0>;
+def LD : DSForm_2<"ld", 58, 0, 1, 0>;
 def LMW : DForm_1<"lmw", 46, 0, 0>;
 def STMW : DForm_3<"stmw", 47, 0, 0>;
 def LFS : DForm_8<"lfs", 48, 0, 0>;
@@ -143,6 +144,7 @@ def STW : DForm_3<"stw", 36, 0, 0>;
 def STWU : DForm_3<"stwu", 37, 0, 0>;
 def STWX : XForm_8<"stwx", 31, 151, 0, 0>;
 def STWUX : XForm_8<"stwux", 31, 183, 0, 0>;
+def STD : DSForm_2<"std", 62, 0, 1, 0>;
 def STFS : DForm_9<"stfs", 52, 0, 0>;
 def STFSX : XForm_28<"stfsx", 31, 663, 0, 0>;
 def STFD : DForm_9<"stfd", 54, 0, 0>;