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| author | Igor Breger <igor.breger@intel.com> | 2017-09-04 09:06:45 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2017-09-04 09:06:45 +0000 |
| commit | 2661ae48c70252b311a5b809df945f1ca3681aad (patch) | |
| tree | 9b2c7541a5513b6184c3ff4b6d49178fb3b75a38 /llvm/lib/Target | |
| parent | 9a087a357a4be44bb40f69f3e23a3e295f70f13e (diff) | |
| download | bcm5719-llvm-2661ae48c70252b311a5b809df945f1ca3681aad.tar.gz bcm5719-llvm-2661ae48c70252b311a5b809df945f1ca3681aad.zip | |
[GlobalISel][X86] G_PHI support.
llvm-svn: 312473
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstructionSelector.cpp | 20 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86LegalizerInfo.cpp | 7 |
2 files changed, 18 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp index be3826a36c5..b43f88232bc 100644 --- a/llvm/lib/Target/X86/X86InstructionSelector.cpp +++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp @@ -85,7 +85,7 @@ private: MachineFunction &MF) const; bool selectCondBranch(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const; - bool selectImplicitDef(MachineInstr &I, MachineRegisterInfo &MRI) const; + bool selectImplicitDefOrPHI(MachineInstr &I, MachineRegisterInfo &MRI) const; // emit insert subreg instruction and insert it before MachineInstr &I bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, @@ -290,13 +290,10 @@ bool X86InstructionSelector::select(MachineInstr &I) const { if (Opcode == TargetOpcode::LOAD_STACK_GUARD) return false; - if (Opcode == TargetOpcode::PHI) - return false; if (I.isCopy()) return selectCopy(I, MRI); - // TODO: handle more cases - LOAD_STACK_GUARD, PHI return true; } @@ -335,7 +332,7 @@ bool X86InstructionSelector::select(MachineInstr &I) const { return true; if (selectCondBranch(I, MRI, MF)) return true; - if (selectImplicitDef(I, MRI)) + if (selectImplicitDefOrPHI(I, MRI)) return true; return false; @@ -1131,10 +1128,11 @@ bool X86InstructionSelector::selectCondBranch(MachineInstr &I, return true; } -bool X86InstructionSelector::selectImplicitDef(MachineInstr &I, - MachineRegisterInfo &MRI) const { +bool X86InstructionSelector::selectImplicitDefOrPHI( + MachineInstr &I, MachineRegisterInfo &MRI) const { - if (I.getOpcode() != TargetOpcode::G_IMPLICIT_DEF) + if (I.getOpcode() != TargetOpcode::G_IMPLICIT_DEF && + I.getOpcode() != TargetOpcode::G_PHI) return false; unsigned DstReg = I.getOperand(0).getReg(); @@ -1150,7 +1148,11 @@ bool X86InstructionSelector::selectImplicitDef(MachineInstr &I, } } - I.setDesc(TII.get(X86::IMPLICIT_DEF)); + if (I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF) + I.setDesc(TII.get(X86::IMPLICIT_DEF)); + else + I.setDesc(TII.get(X86::PHI)); + return true; } diff --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp index f7d7f2398a9..8bceb2c4c6a 100644 --- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp +++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp @@ -52,6 +52,11 @@ void X86LegalizerInfo::setLegalizerInfo32bit() { for (auto Ty : {p0, s1, s8, s16, s32}) setAction({G_IMPLICIT_DEF, Ty}, Legal); + for (auto Ty : {s8, s16, s32, p0}) + setAction({G_PHI, Ty}, Legal); + + setAction({G_PHI, s1}, WidenScalar); + for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) for (auto Ty : {s8, s16, s32}) setAction({BinOp, Ty}, Legal); @@ -118,6 +123,8 @@ void X86LegalizerInfo::setLegalizerInfo64bit() { setAction({G_IMPLICIT_DEF, s64}, Legal); + setAction({G_PHI, s64}, Legal); + for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) setAction({BinOp, s64}, Legal); |
