Fix CodeGen/Generic/2005-05-09-GlobalInPHI.ll, which was reduced from 254.gap.

This caused the "use before a def" assertion on some programs.

With this patch, 254.gap now passes with the PPC backend.

llvm-svn: 21191

1 files changed, 16 insertions, 0 deletions

diff --git a/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp b/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 3d84865b826..d7e131daea3 100644
--- a/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -871,6 +871,16 @@ void PPC32ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
 void PPC32ISel::SelectPHINodes() {
   const TargetInstrInfo &TII = *TM.getInstrInfo();
   const Function &LF = *F->getFunction();  // The LLVM function...
+
+  MachineBasicBlock::iterator MFLRIt = F->begin()->begin();
+  if (GlobalBaseInitialized) {
+    // If we emitted a MFLR for the global base reg, get an iterator to an
+    // instruction after it.
+    while (MFLRIt->getOpcode() != PPC::MFLR)
+      ++MFLRIt;
+    ++MFLRIt;  // step one MI past it.
+  }
+
   for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
     const BasicBlock *BB = I;
     MachineBasicBlock &MBB = *MBBMap[I];
@@ -938,6 +948,12 @@ void PPC32ISel::SelectPHINodes() {
             while (PI != PredMBB->end() && PI->getOpcode() == PPC::PHI)
               ++PI;
 
+            // If this is the entry block, and if the entry block contains a
+            // MFLR instruction, emit this operation after it.  This is needed
+            // because global addresses use it.
+            if (PredMBB == F->begin())
+              PI = MFLRIt;
+
             ValReg = getReg(Val, PredMBB, PI);
           }