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| author | Jozef Kolek <jozef.kolek@imgtec.com> | 2015-02-18 17:15:48 +0000 |
|---|---|---|
| committer | Jozef Kolek <jozef.kolek@imgtec.com> | 2015-02-18 17:15:48 +0000 |
| commit | 1fd6548297791bf548d30518a707541f31c8376b (patch) | |
| tree | d0e9f9f01080fa079319a2f1daa441d54b93c058 /llvm/lib/Target | |
| parent | 83709086674da9eda2b89534c2a292dc9cb82c61 (diff) | |
| download | bcm5719-llvm-1fd6548297791bf548d30518a707541f31c8376b.tar.gz bcm5719-llvm-1fd6548297791bf548d30518a707541f31c8376b.zip | |
[mips][microMIPS] Implement JALX instruction
Differential Revision: http://reviews.llvm.org/D5047
llvm-svn: 229702
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index bf979a0c3a0..e20df2f4e62 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -788,6 +788,7 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">, J_FM_MM<0x35>; def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>; + def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>; } def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>; def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 38a1d03eb02..9a35a2dfb50 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1314,8 +1314,8 @@ let AdditionalPredicates = [NotInMicroMips] in { def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; } -// FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32. -def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6; +def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>, + ISA_MIPS32_NOT_32R6_64R6; def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>, ISA_MIPS1_NOT_32R6_64R6; def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>, |
