summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
diff options
context:
space:
mode:
authorJim Grosbach <grosbach@apple.com>2011-12-13 20:50:38 +0000
committerJim Grosbach <grosbach@apple.com>2011-12-13 20:50:38 +0000
commit1f1a3598c2c5697fc0fae4eda2db1a7b33b799ab (patch)
tree1fabb2e614763ce8ea86a673aa5b00fdc58fadab /llvm/lib/Target
parent4b0844e191ac14f60df1339ed53013c33129f26b (diff)
downloadbcm5719-llvm-1f1a3598c2c5697fc0fae4eda2db1a7b33b799ab.tar.gz
bcm5719-llvm-1f1a3598c2c5697fc0fae4eda2db1a7b33b799ab.zip
ARM thumb2 parsing of "rsb rd, rn, #0".
rdar://10549741 llvm-svn: 146515
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp10
1 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 35251f02b8e..f6827809cd7 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -4727,12 +4727,18 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
}
}
// Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
- // end. Convert it to a token here.
+ // end. Convert it to a token here. Take care not to convert those
+ // that should hit the Thumb2 encoding.
if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
+ static_cast<ARMOperand*>(Operands[3])->isReg() &&
+ static_cast<ARMOperand*>(Operands[4])->isReg() &&
static_cast<ARMOperand*>(Operands[5])->isImm()) {
ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
- if (CE && CE->getValue() == 0) {
+ if (CE && CE->getValue() == 0 &&
+ (isThumbOne() ||
+ (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
+ isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())))) {
Operands.erase(Operands.begin() + 5);
Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
delete Op;
OpenPOWER on IntegriCloud