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| author | Igor Breger <igor.breger@intel.com> | 2015-10-07 06:31:18 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2015-10-07 06:31:18 +0000 |
| commit | 1a6fd1cc0f3dea144ac6bd6291de48283f990745 (patch) | |
| tree | 6e5f0997e533cf721d0b41e8c194af97039f3511 /llvm/lib/Target | |
| parent | cea0b3b45d503a81f075f94bc9751be0fea131ba (diff) | |
| download | bcm5719-llvm-1a6fd1cc0f3dea144ac6bd6291de48283f990745.tar.gz bcm5719-llvm-1a6fd1cc0f3dea144ac6bd6291de48283f990745.zip | |
AVX512: Change encoding of vpshuflw and vpshufhw instructions. Implement WIG as W0 and not W1, like all other instruction have been implemented.
Add encoding tests.
Differential Revision: http://reviews.llvm.org/D13471
llvm-svn: 249521
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 3c9bcf64848..85a53e11793 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -1842,7 +1842,6 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode, } } - multiclass avx512_vector_fpclass_all<string OpcodeStr, AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd, string broadcast>{ @@ -4149,9 +4148,9 @@ defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd", X86PShufd, avx512vl_i32_info>, EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>; defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw", - X86PShufhw>, EVEX, AVX512XSIi8Base, VEX_W; + X86PShufhw>, EVEX, AVX512XSIi8Base; defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw", - X86PShuflw>, EVEX, AVX512XDIi8Base, VEX_W; + X86PShuflw>, EVEX, AVX512XDIi8Base; multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> { let Predicates = [HasBWI] in |
