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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-15 11:47:48 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-15 11:47:48 +0000 |
| commit | 1794cdc4813e2ef6843c2e9e37c2888bca14d33f (patch) | |
| tree | 07c9d07e2c636189e3d279ec044d7b7bbed9c89b /llvm/lib/Target | |
| parent | 0c1e0dbb96d5fe93909c175dfd2da939ccf1e173 (diff) | |
| download | bcm5719-llvm-1794cdc4813e2ef6843c2e9e37c2888bca14d33f.tar.gz bcm5719-llvm-1794cdc4813e2ef6843c2e9e37c2888bca14d33f.zip | |
Fix code causing fallthrough warnings in the PPC back end.
llvm-svn: 320806
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCMIPeephole.cpp | 5 |
4 files changed, 7 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index cf5c3e8b5c6..5e7a9335968 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -2224,6 +2224,7 @@ public: if (CmpInGPR == ICGPR_Sext || CmpInGPR == ICGPR_SextI32 || CmpInGPR == ICGPR_SextI64) return nullptr; + LLVM_FALLTHROUGH; case ISD::SIGN_EXTEND: if (CmpInGPR == ICGPR_Zext || CmpInGPR == ICGPR_ZextI32 || CmpInGPR == ICGPR_ZextI64) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 5c8ef7f1730..ac864baffd6 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -13045,6 +13045,7 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, return std::make_pair(0U, &PPC::QSRCRegClass); if (Subtarget.hasAltivec()) return std::make_pair(0U, &PPC::VRRCRegClass); + break; case 'y': // crrc return std::make_pair(0U, &PPC::CRRCRegClass); } diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index e047179586e..879bb4c797e 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2415,6 +2415,7 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI, NewImm = Addend + SExtImm; break; } + return false; } case PPC::RLDICL: case PPC::RLDICLo: diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp index 45647a2c36b..64c5e4ebb87 100644 --- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp @@ -774,7 +774,7 @@ bool PPCMIPeephole::simplifyCode(void) { // Eliminate all the TOC save instructions which are redundant. Simplified |= eliminateRedundantTOCSaves(TOCSaves); // We try to eliminate redundant compare instruction. - //Simplified |= eliminateRedundantCompare(); + Simplified |= eliminateRedundantCompare(); return Simplified; } @@ -1025,6 +1025,9 @@ bool PPCMIPeephole::eliminateRedundantTOCSaves( // bge 0, .LBB0_4 bool PPCMIPeephole::eliminateRedundantCompare(void) { + // FIXME: this transformation is causing miscompiles. Disabling it for now + // until we can resolve the issue. + return false; bool Simplified = false; for (MachineBasicBlock &MBB2 : *MF) { |

