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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-07-18 17:36:46 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-07-18 17:36:46 +0000
commit14412ef07afefdb7711ed402dd80c3e08af95525 (patch)
tree8a50511f27619ee2226c3edaedef6de8a2d4bc0b /llvm/lib/Target
parent4661a958d8362ed272a2767eca3638f053264831 (diff)
downloadbcm5719-llvm-14412ef07afefdb7711ed402dd80c3e08af95525.tar.gz
bcm5719-llvm-14412ef07afefdb7711ed402dd80c3e08af95525.zip
[Hexagon] Handle returning small structures by value
This is not compliant with the official ABI, but allows experimentation with calling conventions. llvm-svn: 275825
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelLowering.cpp8
1 files changed, 7 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 2a5d7d49be7..cdd4c2f8617 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -447,7 +447,13 @@ static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
if (LocVT == MVT::i32 || LocVT == MVT::f32) {
- if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
+ // Note that use of registers beyond R1 is not ABI compliant. However there
+ // are (experimental) IR passes which generate internal functions that
+ // return structs using these additional registers.
+ static const uint16_t RegList[] = { Hexagon::R0, Hexagon::R1,
+ Hexagon::R2, Hexagon::R3,
+ Hexagon::R4, Hexagon::R5};
+ if (unsigned Reg = State.AllocateReg(RegList)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
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