diff options
| author | Gadi Haber <gadi.haber@intel.com> | 2017-06-27 15:05:13 +0000 |
|---|---|---|
| committer | Gadi Haber <gadi.haber@intel.com> | 2017-06-27 15:05:13 +0000 |
| commit | 13759a7ed62a362bc3d7455da8b96279e545cdc6 (patch) | |
| tree | 2090b37ec2372cd62bbda9fca89ec5c157b44be7 /llvm/lib/Target | |
| parent | a179d25b99fec680d2430a07b6a35254c548e298 (diff) | |
| download | bcm5719-llvm-13759a7ed62a362bc3d7455da8b96279e545cdc6.tar.gz bcm5719-llvm-13759a7ed62a362bc3d7455da8b96279e545cdc6.zip | |
Updated and extended the information about each instruction in HSW and SNB to include the following data:
•static latency
•number of uOps from which the instructions consists
•all ports used by the instruction
Reviewers:
RKSimon
zvi
aymanmus
m_zuckerman
Differential Revision: https://reviews.llvm.org/D33897
llvm-svn: 306414
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 4551 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 2308 |
2 files changed, 5225 insertions, 1634 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 03c8ccb53af..8b9f3b9b2e6 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -23,8 +23,8 @@ def HaswellModel : SchedMachineModel { // Based on the LSD (loop-stream detector) queue size and benchmarking data. let LoopMicroOpBufferSize = 50; - // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow - // the scheduler to assign a default model to unrecognized opcodes. + // This flag is set to allow the scheduler to assign a default model to + // unrecognized opcodes. let CompleteModel = 0; } @@ -267,1914 +267,3251 @@ def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; } def : WriteRes<WriteFence, [HWPort23, HWPort4]>; def : WriteRes<WriteNop, []>; -//================ Exceptions ================// - -//-- Specific Scheduling Models --// - -// Starting with P0. -def WriteP0 : SchedWriteRes<[HWPort0]>; - -def WriteP0_P1_Lat4 : SchedWriteRes<[HWPort0, HWPort1]> { - let Latency = 4; - let NumMicroOps = 2; - let ResourceCycles = [1, 1]; -} +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// -def WriteP0_P1_Lat4Ld : SchedWriteRes<[HWPort0, HWPort1, HWPort23]> { - let Latency = 8; +// HADD, HSUB PS/PD +// x,x / v,v,v. +def : WriteRes<WriteFHAdd, [HWPort1, HWPort5]> { + let Latency = 5; let NumMicroOps = 3; - let ResourceCycles = [1, 1, 1]; + let ResourceCycles = [1, 2]; } -def WriteP01 : SchedWriteRes<[HWPort01]>; +// x,m / v,v,m. +def : WriteRes<WriteFHAddLd, [HWPort1, HWPort5, HWPort23]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1, 2, 1]; +} -def Write2P01 : SchedWriteRes<[HWPort01]> { - let NumMicroOps = 2; +// PHADD|PHSUB (S) W/D. +// v <- v,v. +def : WriteRes<WritePHAdd, [HWPort1, HWPort5]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1, 2]; } -def Write3P01 : SchedWriteRes<[HWPort01]> { +// v <- v,m. +def : WriteRes<WritePHAddLd, [HWPort1, HWPort5, HWPort23]> { + let Latency = 6; let NumMicroOps = 3; + let ResourceCycles = [1, 2, 1]; } -def WriteP015 : SchedWriteRes<[HWPort015]>; +// Remaining instrs. -def WriteP01_P5 : SchedWriteRes<[HWPort01, HWPort5]> { - let NumMicroOps = 2; +def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> { + let Latency = 0; + let NumMicroOps = 1; + let ResourceCycles = [1]; } -def WriteP06 : SchedWriteRes<[HWPort06]>; - -def Write2P06 : SchedWriteRes<[HWPort06]> { - let Latency = 1; +def: InstRW<[HWWriteResGroup0], (instregex "LDDQUrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVD64from64rm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVD64rm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVD64to64rm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVQ64rm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOV32rm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOV64toPQIrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOV8rm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVAPDrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVAPSrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVDDUPrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVDI2PDIrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVDQArm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVDQUrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVNTDQArm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVSHDUPrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVSLDUPrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVSSrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVSX32rm16")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVSX32rm8")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVUPDrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVUPSrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVZX32rm16")>; +def: InstRW<[HWWriteResGroup0], (instregex "MOVZX32rm8")>; +def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHNTA")>; +def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHT0")>; +def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHT1")>; +def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHT2")>; +def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTF128")>; +def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTI128")>; +def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSDYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSSrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSSrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VLDDQUYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VLDDQUrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOV64toPQIrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPDYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPDrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPSYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPSrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDDUPYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDDUPrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDI2PDIrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQAYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQArm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQUYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQUrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVNTDQAYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVNTDQArm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVQI2PQIrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVSDrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVSHDUPYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVSHDUPrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVSLDUPYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVSLDUPrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVSSrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPDYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPDrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPSYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPSrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTDYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTDrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTQYrm")>; +def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTQrm")>; + +def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> { + let Latency = 0; let NumMicroOps = 2; - let ResourceCycles = [2]; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVD64from64rm")>; +def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVD64mr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVNTQmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVQ64mr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOV64mr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOV8mi")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOV8mr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVAPDmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVAPSmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVDQAmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVDQUmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVHPDmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVHPSmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVLPDmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVLPSmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVNTDQmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVNTI_64mr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVNTImr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVNTPDmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVNTPSmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVPDI2DImr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVPQI2QImr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVPQIto64mr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVSSmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVUPDmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "MOVUPSmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VEXTRACTF128mr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VEXTRACTI128mr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPDYmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPDmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPSYmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPSmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQAYmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQAmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQUYmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQUmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVHPDmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVHPSmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVLPDmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVLPSmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTDQYmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTDQmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPDYmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPDmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPSYmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPSmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVPDI2DImr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVPQI2QImr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVPQIto64mr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVSDmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVSSmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPDYmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPDmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPSYmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPSmr")>; +def: InstRW<[HWWriteResGroup1], (instregex "VMPTRSTm")>; + +def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; } - -def Write3P06_Lat2 : SchedWriteRes<[HWPort06]> { - let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [3]; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_MOVD64from64rr")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_MOVD64grr")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PMOVMSKBrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLDri")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLDrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLQri")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLQrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLWri")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLWrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRADri")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRADrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRAWri")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRAWrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLDri")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLDrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLQri")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLQrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLWri")>; +def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLWrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "MOVPDI2DIrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "MOVPQIto64rr")>; +def: InstRW<[HWWriteResGroup2], (instregex "PSLLDri")>; +def: InstRW<[HWWriteResGroup2], (instregex "PSLLQri")>; +def: InstRW<[HWWriteResGroup2], (instregex "PSLLWri")>; +def: InstRW<[HWWriteResGroup2], (instregex "PSRADri")>; +def: InstRW<[HWWriteResGroup2], (instregex "PSRAWri")>; +def: InstRW<[HWWriteResGroup2], (instregex "PSRLDri")>; +def: InstRW<[HWWriteResGroup2], (instregex "PSRLQri")>; +def: InstRW<[HWWriteResGroup2], (instregex "PSRLWri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VMOVPDI2DIrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "VMOVPQIto64rr")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLDri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLDrm")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLQri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLQrm")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQYrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLWri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSLLWrm")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSRADYri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSRADri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSRAWYri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSRAWri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLDYri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLDri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLQYri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLQri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLVQYrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLVQrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLWYri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VPSRLWri")>; +def: InstRW<[HWWriteResGroup2], (instregex "VTESTPDYrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "VTESTPDrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "VTESTPSYrr")>; +def: InstRW<[HWWriteResGroup2], (instregex "VTESTPSrr")>; + +def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; } +def: InstRW<[HWWriteResGroup3], (instregex "MASKMOVDQU64")>; +def: InstRW<[HWWriteResGroup3], (instregex "MMX_MASKMOVQ64")>; -def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { - let NumMicroOps = 2; +def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; } - -def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { - let NumMicroOps = 3; - let ResourceCycles = [2, 1]; +def: InstRW<[HWWriteResGroup4], (instregex "ANDNPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "ANDNPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "ANDPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "ANDPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "INSERTPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "KORTESTBrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64to64rr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVQ2DQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PALIGNR64irr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PSHUFBrr64")>; +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PSHUFWri")>; +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHBWirr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHDQirr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHWDirr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLBWirr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLDQirr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLWDirr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MOV64toPQIrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MOVAPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MOVAPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MOVDDUPrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MOVDI2PDIrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MOVHLPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MOVLHPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MOVSDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MOVSHDUPrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MOVSLDUPrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MOVSSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MOVUPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "MOVUPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "ORPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "ORPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PACKSSDWrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PACKSSWBrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PACKUSDWrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PACKUSWBrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PALIGNRrri")>; +def: InstRW<[HWWriteResGroup4], (instregex "PBLENDWrri")>; +def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBWrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXDQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXWDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXWQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBWrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXDQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXWDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXWQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PSHUFBrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PSHUFDri")>; +def: InstRW<[HWWriteResGroup4], (instregex "PSHUFHWri")>; +def: InstRW<[HWWriteResGroup4], (instregex "PSHUFLWri")>; +def: InstRW<[HWWriteResGroup4], (instregex "PSLLDQri")>; +def: InstRW<[HWWriteResGroup4], (instregex "PSRLDQri")>; +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHBWrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHDQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHQDQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHWDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLBWrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLDQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLQDQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLWDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "SHUFPDrri")>; +def: InstRW<[HWWriteResGroup4], (instregex "SHUFPSrri")>; +def: InstRW<[HWWriteResGroup4], (instregex "UNPCKHPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "UNPCKHPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "UNPCKLPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "UNPCKLPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VANDNPDYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VANDNPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VANDNPSYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VANDNPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VANDPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VANDPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VANDPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VBROADCASTSSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VGATHERQPSZrm")>; +def: InstRW<[HWWriteResGroup4], (instregex "VINSERTPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOV64toPQIrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOV64toPQIrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVDDUPYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVDDUPrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVHLPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVLHPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVSDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVSHDUPYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVSHDUPrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVSLDUPYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVSLDUPrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVSSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VORPDYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VORPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VORPSYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VORPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSDWYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSDWrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSWBYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSWBrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSDWYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSDWrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSWBYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSWBrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPALIGNRYrri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPALIGNRrri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPBLENDWYrri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPBLENDWrri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPBROADCASTDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPBROADCASTQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDrm")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSrm")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBWrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXDQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXWDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXWQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBWrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXDQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXWDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXWQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFBrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFBrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFDYri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFDri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFHWri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFLWYri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFLWri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPSLLDQYri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPSLLDQri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPSRLDQYri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPSRLDQri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHBWYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHBWrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHDQYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHDQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHQDQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHWDYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHWDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLBWrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLDQYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLDQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLQDQYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLQDQrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLWDYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLWDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPDYrri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPDrri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPSYrri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPSrri")>; +def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPDYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPSYrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VXORPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "VXORPSrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "XORPDrr")>; +def: InstRW<[HWWriteResGroup4], (instregex "XORPSrr")>; + +def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; } +def: InstRW<[HWWriteResGroup5], (instregex "JMP64r")>; -def Write2P0156_Lat2 : SchedWriteRes<[HWPort0156]> { - let Latency = 2; - let ResourceCycles = [2]; -} -def Write2P0156_Lat2Ld : SchedWriteRes<[HWPort0156, HWPort23]> { - let Latency = 6; - let ResourceCycles = [2, 1]; +def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; } +def: InstRW<[HWWriteResGroup6], (instregex "FINCSTP")>; +def: InstRW<[HWWriteResGroup6], (instregex "FNOP")>; -def Write5P0156 : SchedWriteRes<[HWPort0156]> { - let NumMicroOps = 5; - let ResourceCycles = [5]; +def HWWriteResGroup7 : SchedWriteRes<[HWPort0]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; } - -def WriteP0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> { +def: InstRW<[HWWriteResGroup7], (instregex "BT32ri8")>; +def: InstRW<[HWWriteResGroup7], (instregex "BT32rr")>; +def: InstRW<[HWWriteResGroup7], (instregex "BTC32ri8")>; +def: InstRW<[HWWriteResGroup7], (instregex "BTC32rr")>; +def: InstRW<[HWWriteResGroup7], (instregex "BTR32ri8")>; +def: InstRW<[HWWriteResGroup7], (instregex "BTR32rr")>; +def: InstRW<[HWWriteResGroup7], (instregex "BTS32ri8")>; +def: InstRW<[HWWriteResGroup7], (instregex "BTS32rr")>; +def: InstRW<[HWWriteResGroup7], (instregex "CDQ")>; +def: InstRW<[HWWriteResGroup7], (instregex "CQO")>; +def: InstRW<[HWWriteResGroup7], (instregex "RORX32ri")>; +def: InstRW<[HWWriteResGroup7], (instregex "RORX64ri")>; +def: InstRW<[HWWriteResGroup7], (instregex "SAR32ri")>; +def: InstRW<[HWWriteResGroup7], (instregex "SAR64r1")>; +def: InstRW<[HWWriteResGroup7], (instregex "SAR8r1")>; +def: InstRW<[HWWriteResGroup7], (instregex "SAR8ri")>; +def: InstRW<[HWWriteResGroup7], (instregex "SARX32rr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SARX64rr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETAEr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETBr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETEr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETGEr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETGr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETLEr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETLr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETNEr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETNOr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETNPr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETNSr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETOr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETPr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SETSr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SHL32ri")>; +def: InstRW<[HWWriteResGroup7], (instregex "SHL64r1")>; +def: InstRW<[HWWriteResGroup7], (instregex "SHL8r1")>; +def: InstRW<[HWWriteResGroup7], (instregex "SHL8ri")>; +def: InstRW<[HWWriteResGroup7], (instregex "SHLX32rr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SHLX64rr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SHR32ri")>; +def: InstRW<[HWWriteResGroup7], (instregex "SHR64r1")>; +def: InstRW<[HWWriteResGroup7], (instregex "SHR8r1")>; +def: InstRW<[HWWriteResGroup7], (instregex "SHR8ri")>; +def: InstRW<[HWWriteResGroup7], (instregex "SHRX32rr")>; +def: InstRW<[HWWriteResGroup7], (instregex "SHRX64rr")>; + +def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> { let Latency = 1; - let ResourceCycles = [1, 2, 1]; + let NumMicroOps = 1; + let ResourceCycles = [1]; } - -def Write2P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> { +def: InstRW<[HWWriteResGroup8], (instregex "ANDN32rr")>; +def: InstRW<[HWWriteResGroup8], (instregex "ANDN64rr")>; +def: InstRW<[HWWriteResGroup8], (instregex "BLSI32rr")>; +def: InstRW<[HWWriteResGroup8], (instregex "BLSI64rr")>; +def: InstRW<[HWWriteResGroup8], (instregex "BLSMSK32rr")>; +def: InstRW<[HWWriteResGroup8], (instregex "BLSMSK64rr")>; +def: InstRW<[HWWriteResGroup8], (instregex "BLSR32rr")>; +def: InstRW<[HWWriteResGroup8], (instregex "BLSR64rr")>; +def: InstRW<[HWWriteResGroup8], (instregex "BZHI32rr")>; +def: InstRW<[HWWriteResGroup8], (instregex "BZHI64rr")>; +def: InstRW<[HWWriteResGroup8], (instregex "LEA64_32r")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSBrr64")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSDrr64")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSWrr64")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDBirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDDirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDQirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDSBirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDSWirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDUSBirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDUSWirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDWirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PAVGBirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PAVGWirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQBirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQDirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQWirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTBirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTDirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTWirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMAXSWirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMAXUBirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMINSWirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMINUBirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNBrr64")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNDrr64")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNWrr64")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBBirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBDirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBQirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBSBirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBSWirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBUSBirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBUSWirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBWirr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PABSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PABSDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PABSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PADDBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PADDDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PADDQrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PADDSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PADDSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PADDUSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PADDUSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PADDWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PAVGBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PAVGWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQQrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PMAXSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PMAXSDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PMAXSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PMAXUBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PMAXUDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PMAXUWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PMINSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PMINSDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PMINSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PMINUBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PMINUDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PMINUWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PSIGNBrr128")>; +def: InstRW<[HWWriteResGroup8], (instregex "PSIGNDrr128")>; +def: InstRW<[HWWriteResGroup8], (instregex "PSIGNWrr128")>; +def: InstRW<[HWWriteResGroup8], (instregex "PSUBBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PSUBDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PSUBQrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PSUBSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PSUBSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PSUBUSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PSUBUSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "PSUBWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VMASKMOVPSYrm")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPABSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPABSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPABSDYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPABSDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPABSWYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPABSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPADDBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPADDBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPADDDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPADDDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPADDQYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPADDQrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPADDSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPADDSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSBYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSWYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPADDWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPAVGBYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPAVGBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPAVGWYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPAVGWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQQrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTBYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTDYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTWYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSBYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSDYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSWYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUBYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUDYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUWYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMINSBYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMINSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMINSDYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMINSDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMINSWYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMINSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMINUBYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMINUBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMINUDYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMINUDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMINUWYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPMINUWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBYrr256")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBrr128")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDYrr256")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDrr128")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWYrr256")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWrr128")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBBYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBDYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBDrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBQYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBQrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSBYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSWYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSBYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSBrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSWYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSWrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBWYrr")>; +def: InstRW<[HWWriteResGroup8], (instregex "VPSUBWrr")>; + +def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> { let Latency = 1; - let ResourceCycles = [2, 2, 1]; + let NumMicroOps = 1; + let ResourceCycles = [1]; } - -def Write3P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> { +def: InstRW<[HWWriteResGroup9], (instregex "BLENDPDrri")>; +def: InstRW<[HWWriteResGroup9], (instregex "BLENDPSrri")>; +def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVD64from64rr")>; +def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVQ64rr")>; +def: InstRW<[HWWriteResGroup9], (instregex "MMX_PANDNirr")>; +def: InstRW<[HWWriteResGroup9], (instregex "MMX_PANDirr")>; +def: InstRW<[HWWriteResGroup9], (instregex "MMX_PORirr")>; +def: InstRW<[HWWriteResGroup9], (instregex "MMX_PXORirr")>; +def: InstRW<[HWWriteResGroup9], (instregex "MOVDQArr")>; +def: InstRW<[HWWriteResGroup9], (instregex "MOVDQUrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "MOVPQI2QIrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "PANDNrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "PANDrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "PORrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "PXORrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPDYrri")>; +def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPDrri")>; +def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPSYrri")>; +def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPSrri")>; +def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQAYrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQArr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUYrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VMOVPQI2QIrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VMOVZPQILo2PQIrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VPANDNYrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VPANDNrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VPANDYrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VPANDrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDDYrri")>; +def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDDrri")>; +def: InstRW<[HWWriteResGroup9], (instregex "VPORYrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VPORrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VPXORYrr")>; +def: InstRW<[HWWriteResGroup9], (instregex "VPXORrr")>; + +def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> { let Latency = 1; - let ResourceCycles = [3, 2, 1]; + let NumMicroOps = 1; + let ResourceCycles = [1]; } - -// Starting with P1. -def WriteP1 : SchedWriteRes<[HWPort1]>; - -def WriteP1_P23 : SchedWriteRes<[HWPort1, HWPort23]> { +def: InstRW<[HWWriteResGroup10], (instregex "ADD32ri8")>; +def: InstRW<[HWWriteResGroup10], (instregex "ADD32rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "ADD8ri")>; +def: InstRW<[HWWriteResGroup10], (instregex "ADD8rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "AND32ri")>; +def: InstRW<[HWWriteResGroup10], (instregex "AND64ri8")>; +def: InstRW<[HWWriteResGroup10], (instregex "AND64rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "AND8ri")>; +def: InstRW<[HWWriteResGroup10], (instregex "AND8rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "CBW")>; +def: InstRW<[HWWriteResGroup10], (instregex "CLC")>; +def: InstRW<[HWWriteResGroup10], (instregex "CMC")>; +def: InstRW<[HWWriteResGroup10], (instregex "CMP16ri8")>; +def: InstRW<[HWWriteResGroup10], (instregex "CMP32i32")>; +def: InstRW<[HWWriteResGroup10], (instregex "CMP64rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "CMP8ri")>; +def: InstRW<[HWWriteResGroup10], (instregex "CMP8rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "CWDE")>; +def: InstRW<[HWWriteResGroup10], (instregex "DEC64r")>; +def: InstRW<[HWWriteResGroup10], (instregex "DEC8r")>; +def: InstRW<[HWWriteResGroup10], (instregex "INC64r")>; +def: InstRW<[HWWriteResGroup10], (instregex "INC8r")>; +def: InstRW<[HWWriteResGroup10], (instregex "LAHF")>; +def: InstRW<[HWWriteResGroup10], (instregex "MOV32rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "MOV8ri")>; +def: InstRW<[HWWriteResGroup10], (instregex "MOV8rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "MOVSX32rr16")>; +def: InstRW<[HWWriteResGroup10], (instregex "MOVSX32rr8")>; +def: InstRW<[HWWriteResGroup10], (instregex "MOVZX32rr16")>; +def: InstRW<[HWWriteResGroup10], (instregex "MOVZX32rr8")>; +def: InstRW<[HWWriteResGroup10], (instregex "NEG64r")>; +def: InstRW<[HWWriteResGroup10], (instregex "NEG8r")>; +def: InstRW<[HWWriteResGroup10], (instregex "NOOP")>; +def: InstRW<[HWWriteResGroup10], (instregex "NOT64r")>; +def: InstRW<[HWWriteResGroup10], (instregex "NOT8r")>; +def: InstRW<[HWWriteResGroup10], (instregex "OR64ri8")>; +def: InstRW<[HWWriteResGroup10], (instregex "OR64rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "OR8ri")>; +def: InstRW<[HWWriteResGroup10], (instregex "OR8rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "SAHF")>; +def: InstRW<[HWWriteResGroup10], (instregex "SGDT64m")>; +def: InstRW<[HWWriteResGroup10], (instregex "SIDT64m")>; +def: InstRW<[HWWriteResGroup10], (instregex "SLDT16m")>; +def: InstRW<[HWWriteResGroup10], (instregex "SMSW16m")>; +def: InstRW<[HWWriteResGroup10], (instregex "STC")>; +def: InstRW<[HWWriteResGroup10], (instregex "STRm")>; +def: InstRW<[HWWriteResGroup10], (instregex "SUB64ri8")>; +def: InstRW<[HWWriteResGroup10], (instregex "SUB64rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "SUB8ri")>; +def: InstRW<[HWWriteResGroup10], (instregex "SUB8rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "SYSCALL")>; +def: InstRW<[HWWriteResGroup10], (instregex "TEST64rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>; +def: InstRW<[HWWriteResGroup10], (instregex "TEST8rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "XCHG64rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "XOR32rr")>; +def: InstRW<[HWWriteResGroup10], (instregex "XOR64ri8")>; +def: InstRW<[HWWriteResGroup10], (instregex "XOR8ri")>; +def: InstRW<[HWWriteResGroup10], (instregex "XOR8rr")>; + +def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 1; let NumMicroOps = 2; -} -def WriteP1_Lat3 : SchedWriteRes<[HWPort1]> { - let Latency = 3; -} -def WriteP1_Lat3Ld : SchedWriteRes<[HWPort1, HWPort23]> { - let Latency = 7; -} - -def Write2P1 : SchedWriteRes<[HWPort1]> { + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup11], (instregex "CVTPS2PDrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "CVTSS2SDrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLDrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLQrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLWrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRADrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRAWrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLDrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLQrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLWrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VCVTPH2PSYrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VCVTPH2PSrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VCVTPS2PDrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VCVTSS2SDrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VPSLLDYri")>; +def: InstRW<[HWWriteResGroup11], (instregex "VPSLLQYri")>; +def: InstRW<[HWWriteResGroup11], (instregex "VPSLLVQYrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VPSLLVQrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VPSLLWYri")>; +def: InstRW<[HWWriteResGroup11], (instregex "VPSRADYrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VPSRAWYrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VPSRLDYrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VPSRLQYrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VPSRLVQYrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VPSRLVQrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VPSRLWYrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VTESTPDYrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VTESTPDrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VTESTPSYrm")>; +def: InstRW<[HWWriteResGroup11], (instregex "VTESTPSrm")>; + +def HWWriteResGroup12 : SchedWriteRes<[HWPort5,HWPort23]> { + let Latency = 1; let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def Write2P1_P23 : SchedWriteRes<[HWPort1, HWPort23]> { - let NumMicroOps = 3; - let ResourceCycles = [2, 1]; -} -def WriteP15 : SchedWriteRes<[HWPort15]>; -def WriteP15Ld : SchedWriteRes<[HWPort15, HWPort23]> { - let Latency = 4; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup12], (instregex "ANDNPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "ANDNPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "ANDPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "ANDPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "INSERTPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PALIGNR64irm")>; +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PINSRWirmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PSHUFBrm64")>; +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PSHUFWmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKHBWirm")>; +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKHDQirm")>; +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKHWDirm")>; +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKLBWirm")>; +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKLDQirm")>; +def: InstRW<[HWWriteResGroup12], (instregex "MMX_PUNPCKLWDirm")>; +def: InstRW<[HWWriteResGroup12], (instregex "MOVHPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "MOVHPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "MOVLPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "MOVLPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "ORPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "ORPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PACKSSDWrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PACKSSWBrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PACKUSDWrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PACKUSWBrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PALIGNRrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "PBLENDWrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "PINSRBrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PINSRDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PINSRQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PINSRWrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXBDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXBQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXBWrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXDQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXWDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PMOVSXWQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXBDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXBQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXBWrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXDQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXWDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PMOVZXWQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PSHUFBrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PSHUFDmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "PSHUFHWmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "PSHUFLWmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKHBWrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKHDQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKHQDQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKHWDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKLBWrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKLDQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKLQDQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "PUNPCKLWDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "SHUFPDrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "SHUFPSrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "UNPCKHPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "UNPCKHPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "UNPCKLPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "UNPCKLPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VANDNPDYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VANDNPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VANDNPSYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VANDNPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VANDPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VANDPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VANDPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VANDPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VINSERTPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VMOVHPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VMOVHPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VMOVLPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VMOVLPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VORPDYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VORPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VORPSYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VORPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPACKSSDWYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPACKSSDWrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPACKSSWBYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPACKSSWBrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPACKUSDWYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPACKUSDWrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPACKUSWBYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPACKUSWBrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPALIGNRYrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPALIGNRrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPBLENDWYrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPBLENDWrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPDYri")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPDmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPDmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPDri")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPSYri")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPSmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPSmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPERMILPSri")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPINSRBrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPINSRDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPINSRQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPINSRWrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXBDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXBQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXBWrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXDQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXWDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVSXWQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXBDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXBQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXBWrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXDQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXWDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPMOVZXWQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFBrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFBrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFDYmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFDmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFHWmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFHWmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFLWYmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPSHUFLWmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHBWYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHBWrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHDQYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHDQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHQDQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHQDQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHWDYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKHWDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLBWrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLBWrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLDQYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLDQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLQDQYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLQDQrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLWDYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VPUNPCKLWDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VSHUFPDYrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VSHUFPDrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VSHUFPSYrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VSHUFPSrmi")>; +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKHPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKHPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKHPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKHPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKLPDYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKLPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKLPSYrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VUNPCKLPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VXORPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VXORPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VXORPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "VXORPSrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "XORPDrm")>; +def: InstRW<[HWWriteResGroup12], (instregex "XORPSrm")>; + +def HWWriteResGroup13 : SchedWriteRes<[HWPort6,HWPort23]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; } +def: InstRW<[HWWriteResGroup13], (instregex "FARJMP64")>; +def: InstRW<[HWWriteResGroup13], (instregex "JMP64m")>; -def WriteP1_P5_Lat4 : SchedWriteRes<[HWPort1, HWPort5]> { - let Latency = 4; +def HWWriteResGroup14 : SchedWriteRes<[HWPort23,HWPort0]> { + let Latency = 1; let NumMicroOps = 2; - let ResourceCycles = [1, 1]; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup14], (instregex "BT64mi8")>; +def: InstRW<[HWWriteResGroup14], (instregex "RORX32mi")>; +def: InstRW<[HWWriteResGroup14], (instregex "RORX64mi")>; +def: InstRW<[HWWriteResGroup14], (instregex "SARX32rm")>; +def: InstRW<[HWWriteResGroup14], (instregex "SARX64rm")>; +def: InstRW<[HWWriteResGroup14], (instregex "SHLX32rm")>; +def: InstRW<[HWWriteResGroup14], (instregex "SHLX64rm")>; +def: InstRW<[HWWriteResGroup14], (instregex "SHRX32rm")>; +def: InstRW<[HWWriteResGroup14], (instregex "SHRX64rm")>; + +def HWWriteResGroup15 : SchedWriteRes<[HWPort23,HWPort15]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup15], (instregex "ANDN32rm")>; +def: InstRW<[HWWriteResGroup15], (instregex "ANDN64rm")>; +def: InstRW<[HWWriteResGroup15], (instregex "BLSI32rm")>; +def: InstRW<[HWWriteResGroup15], (instregex "BLSI64rm")>; +def: InstRW<[HWWriteResGroup15], (instregex "BLSMSK32rm")>; +def: InstRW<[HWWriteResGroup15], (instregex "BLSMSK64rm")>; +def: InstRW<[HWWriteResGroup15], (instregex "BLSR32rm")>; +def: InstRW<[HWWriteResGroup15], (instregex "BLSR64rm")>; +def: InstRW<[HWWriteResGroup15], (instregex "BZHI32rm")>; +def: InstRW<[HWWriteResGroup15], (instregex "BZHI64rm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PABSBrm64")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PABSDrm64")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PABSWrm64")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDBirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDDirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDQirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDSBirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDSWirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDUSBirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDUSWirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PADDWirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PAVGBirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PAVGWirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPEQBirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPEQDirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPEQWirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPGTBirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPGTDirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PCMPGTWirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PMAXSWirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PMAXUBirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PMINSWirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PMINUBirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSIGNBrm64")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSIGNDrm64")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSIGNWrm64")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBBirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBDirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBQirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBSBirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBSWirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBUSBirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBUSWirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MMX_PSUBWirm")>; +def: InstRW<[HWWriteResGroup15], (instregex "MOVBE64rm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PABSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PABSDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PABSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PADDBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PADDDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PADDQrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PADDSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PADDSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PADDUSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PADDUSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PADDWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PAVGBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PAVGWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PCMPEQBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PCMPEQDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PCMPEQQrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PCMPEQWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PCMPGTBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PCMPGTDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PCMPGTWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PMAXSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PMAXSDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PMAXSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PMAXUBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PMAXUDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PMAXUWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PMINSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PMINSDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PMINSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PMINUBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PMINUDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PMINUWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PSIGNBrm128")>; +def: InstRW<[HWWriteResGroup15], (instregex "PSIGNDrm128")>; +def: InstRW<[HWWriteResGroup15], (instregex "PSIGNWrm128")>; +def: InstRW<[HWWriteResGroup15], (instregex "PSUBBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PSUBDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PSUBQrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PSUBSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PSUBSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PSUBUSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PSUBUSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "PSUBWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPABSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPABSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPABSDYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPABSDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPABSWYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPABSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDQYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDQrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDUSBYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDUSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDUSWYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDUSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPADDWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPAVGBYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPAVGBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPAVGWYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPAVGWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQQrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQQrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPEQWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTBYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTDYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTWYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPCMPGTWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSBYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSDYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSWYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUBYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUDYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUWYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMAXUWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMINSBYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMINSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMINSDYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMINSDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMINSWYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMINSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMINUBYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMINUBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMINUDYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMINUDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMINUWYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPMINUWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNBYrm256")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNBrm128")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNDYrm256")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNDrm128")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNWYrm256")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSIGNWrm128")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBBYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBDYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBDrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBQYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBQrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBSBYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBSWYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBUSBYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBUSBrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBUSWYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBUSWrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBWYrm")>; +def: InstRW<[HWWriteResGroup15], (instregex "VPSUBWrm")>; + +def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort015]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup16], (instregex "BLENDPDrmi")>; +def: InstRW<[HWWriteResGroup16], (instregex "BLENDPSrmi")>; +def: InstRW<[HWWriteResGroup16], (instregex "MMX_PANDNirm")>; +def: InstRW<[HWWriteResGroup16], (instregex "MMX_PANDirm")>; +def: InstRW<[HWWriteResGroup16], (instregex "MMX_PORirm")>; +def: InstRW<[HWWriteResGroup16], (instregex "MMX_PXORirm")>; +def: InstRW<[HWWriteResGroup16], (instregex "PANDNrm")>; +def: InstRW<[HWWriteResGroup16], (instregex "PANDrm")>; +def: InstRW<[HWWriteResGroup16], (instregex "PORrm")>; +def: InstRW<[HWWriteResGroup16], (instregex "PXORrm")>; +def: InstRW<[HWWriteResGroup16], (instregex "VBLENDPDYrmi")>; +def: InstRW<[HWWriteResGroup16], (instregex "VBLENDPDrmi")>; +def: InstRW<[HWWriteResGroup16], (instregex "VBLENDPSYrmi")>; +def: InstRW<[HWWriteResGroup16], (instregex "VBLENDPSrmi")>; +def: InstRW<[HWWriteResGroup16], (instregex "VINSERTF128rm")>; +def: InstRW<[HWWriteResGroup16], (instregex "VINSERTI128rm")>; +def: InstRW<[HWWriteResGroup16], (instregex "VPANDNYrm")>; +def: InstRW<[HWWriteResGroup16], (instregex "VPANDNrm")>; +def: InstRW<[HWWriteResGroup16], (instregex "VPANDYrm")>; +def: InstRW<[HWWriteResGroup16], (instregex "VPANDrm")>; +def: InstRW<[HWWriteResGroup16], (instregex "VPBLENDDYrmi")>; +def: InstRW<[HWWriteResGroup16], (instregex "VPBLENDDrmi")>; +def: InstRW<[HWWriteResGroup16], (instregex "VPORYrm")>; +def: InstRW<[HWWriteResGroup16], (instregex "VPORrm")>; +def: InstRW<[HWWriteResGroup16], (instregex "VPXORYrm")>; +def: InstRW<[HWWriteResGroup16], (instregex "VPXORrm")>; + +def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort0156]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup17], (instregex "ADD64rm")>; +def: InstRW<[HWWriteResGroup17], (instregex "ADD8rm")>; +def: InstRW<[HWWriteResGroup17], (instregex "AND64rm")>; +def: InstRW<[HWWriteResGroup17], (instregex "AND8rm")>; +def: InstRW<[HWWriteResGroup17], (instregex "CMP64mi8")>; +def: InstRW<[HWWriteResGroup17], (instregex "CMP64mr")>; +def: InstRW<[HWWriteResGroup17], (instregex "CMP64rm")>; +def: InstRW<[HWWriteResGroup17], (instregex "CMP8mi")>; +def: InstRW<[HWWriteResGroup17], (instregex "CMP8mr")>; +def: InstRW<[HWWriteResGroup17], (instregex "CMP8rm")>; +def: InstRW<[HWWriteResGroup17], (instregex "OR64rm")>; +def: InstRW<[HWWriteResGroup17], (instregex "OR8rm")>; +def: InstRW<[HWWriteResGroup17], (instregex "POP64r")>; +def: InstRW<[HWWriteResGroup17], (instregex "SUB64rm")>; +def: InstRW<[HWWriteResGroup17], (instregex "SUB8rm")>; +def: InstRW<[HWWriteResGroup17], (instregex "TEST64rm")>; +def: InstRW<[HWWriteResGroup17], (instregex "TEST8mi")>; +def: InstRW<[HWWriteResGroup17], (instregex "TEST8rm")>; +def: InstRW<[HWWriteResGroup17], (instregex "XOR64rm")>; +def: InstRW<[HWWriteResGroup17], (instregex "XOR8rm")>; + +def HWWriteResGroup18 : SchedWriteRes<[HWPort237,HWPort0156]> { + let Latency = 1; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; } +def: InstRW<[HWWriteResGroup18], (instregex "SFENCE")>; -def WriteP1_P5_Lat4Ld : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> { - let Latency = 8; +def HWWriteResGroup19 : SchedWriteRes<[HWPort4,HWPort5,HWPort237]> { + let Latency = 1; let NumMicroOps = 3; - let ResourceCycles = [1, 1, 1]; -} - -def WriteP1_P5_Lat6 : SchedWriteRes<[HWPort1, HWPort5]> { - let Latency = 6; - let NumMicroOps = 2; - let ResourceCycles = [1, 1]; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup19], (instregex "EXTRACTPSmr")>; +def: InstRW<[HWWriteResGroup19], (instregex "PEXTRBmr")>; +def: InstRW<[HWWriteResGroup19], (instregex "PEXTRDmr")>; +def: InstRW<[HWWriteResGroup19], (instregex "PEXTRQmr")>; +def: InstRW<[HWWriteResGroup19], (instregex "PEXTRWmr")>; +def: InstRW<[HWWriteResGroup19], (instregex "STMXCSR")>; +def: InstRW<[HWWriteResGroup19], (instregex "VEXTRACTPSmr")>; +def: InstRW<[HWWriteResGroup19], (instregex "VPEXTRBmr")>; +def: InstRW<[HWWriteResGroup19], (instregex "VPEXTRDmr")>; +def: InstRW<[HWWriteResGroup19], (instregex "VPEXTRQmr")>; +def: InstRW<[HWWriteResGroup19], (instregex "VPEXTRWmr")>; +def: InstRW<[HWWriteResGroup19], (instregex "VSTMXCSR")>; + +def HWWriteResGroup20 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> { + let Latency = 1; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; } +def: InstRW<[HWWriteResGroup20], (instregex "FNSTCW16m")>; -def WriteP1_P5_Lat6Ld : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> { - let Latency = 10; +def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort237,HWPort0]> { + let Latency = 1; let NumMicroOps = 3; - let ResourceCycles = [1, 1, 1]; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup21], (instregex "SETAEm")>; +def: InstRW<[HWWriteResGroup21], (instregex "SETBm")>; +def: InstRW<[HWWriteResGroup21], (instregex "SETEm")>; +def: InstRW<[HWWriteResGroup21], (instregex "SETGEm")>; +def: InstRW<[HWWriteResGroup21], (instregex "SETGm")>; +def: InstRW<[HWWriteResGroup21], (instregex "SETLEm")>; +def: InstRW<[HWWriteResGroup21], (instregex "SETLm")>; +def: InstRW<[HWWriteResGroup21], (instregex "SETNEm")>; +def: InstRW<[HWWriteResGroup21], (instregex "SETNOm")>; +def: InstRW<[HWWriteResGroup21], (instregex "SETNPm")>; +def: InstRW<[HWWriteResGroup21], (instregex "SETNSm")>; +def: InstRW<[HWWriteResGroup21], (instregex "SETOm")>; +def: InstRW<[HWWriteResGroup21], (instregex "SETPm")>; +def: InstRW<[HWWriteResGroup21], (instregex "SETSm")>; + +def HWWriteResGroup22 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> { + let Latency = 1; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; } +def: InstRW<[HWWriteResGroup22], (instregex "MOVBE64mr")>; -// Starting with P2. -def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> { +def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { let Latency = 1; - let ResourceCycles = [2, 1]; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; } +def: InstRW<[HWWriteResGroup23], (instregex "PUSH64i8")>; +def: InstRW<[HWWriteResGroup23], (instregex "PUSH64r")>; +def: InstRW<[HWWriteResGroup23], (instregex "STOSB")>; +def: InstRW<[HWWriteResGroup23], (instregex "STOSL")>; +def: InstRW<[HWWriteResGroup23], (instregex "STOSQ")>; +def: InstRW<[HWWriteResGroup23], (instregex "STOSW")>; -// Starting with P5. -def WriteP5 : SchedWriteRes<[HWPort5]>; -def WriteP5Ld : SchedWriteRes<[HWPort5, HWPort23]> { - let Latency = 5; +def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0]> { + let Latency = 1; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup24], (instregex "BTC64mi8")>; +def: InstRW<[HWWriteResGroup24], (instregex "BTR64mi8")>; +def: InstRW<[HWWriteResGroup24], (instregex "BTS64mi8")>; +def: InstRW<[HWWriteResGroup24], (instregex "SAR64m1")>; +def: InstRW<[HWWriteResGroup24], (instregex "SAR64mi")>; +def: InstRW<[HWWriteResGroup24], (instregex "SAR8m1")>; +def: InstRW<[HWWriteResGroup24], (instregex "SAR8mi")>; +def: InstRW<[HWWriteResGroup24], (instregex "SHL64m1")>; +def: InstRW<[HWWriteResGroup24], (instregex "SHL64mi")>; +def: InstRW<[HWWriteResGroup24], (instregex "SHL8m1")>; +def: InstRW<[HWWriteResGroup24], (instregex "SHL8mi")>; +def: InstRW<[HWWriteResGroup24], (instregex "SHR64m1")>; +def: InstRW<[HWWriteResGroup24], (instregex "SHR64mi")>; +def: InstRW<[HWWriteResGroup24], (instregex "SHR8m1")>; +def: InstRW<[HWWriteResGroup24], (instregex "SHR8mi")>; + +def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { + let Latency = 1; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[HWWriteResGroup25], (instregex "ADD64mi8")>; +def: InstRW<[HWWriteResGroup25], (instregex "ADD64mr")>; +def: InstRW<[HWWriteResGroup25], (instregex "ADD8mi")>; +def: InstRW<[HWWriteResGroup25], (instregex "ADD8mr")>; +def: InstRW<[HWWriteResGroup25], (instregex "AND64mi8")>; +def: InstRW<[HWWriteResGroup25], (instregex "AND64mr")>; +def: InstRW<[HWWriteResGroup25], (instregex "AND8mi")>; +def: InstRW<[HWWriteResGroup25], (instregex "AND8mr")>; +def: InstRW<[HWWriteResGroup25], (instregex "DEC64m")>; +def: InstRW<[HWWriteResGroup25], (instregex "DEC8m")>; +def: InstRW<[HWWriteResGroup25], (instregex "INC64m")>; +def: InstRW<[HWWriteResGroup25], (instregex "INC8m")>; +def: InstRW<[HWWriteResGroup25], (instregex "NEG64m")>; +def: InstRW<[HWWriteResGroup25], (instregex "NEG8m")>; +def: InstRW<[HWWriteResGroup25], (instregex "NOT64m")>; +def: InstRW<[HWWriteResGroup25], (instregex "NOT8m")>; +def: InstRW<[HWWriteResGroup25], (instregex "OR64mi8")>; +def: InstRW<[HWWriteResGroup25], (instregex "OR64mr")>; +def: InstRW<[HWWriteResGroup25], (instregex "OR8mi")>; +def: InstRW<[HWWriteResGroup25], (instregex "OR8mr")>; +def: InstRW<[HWWriteResGroup25], (instregex "POP64rmm")>; +def: InstRW<[HWWriteResGroup25], (instregex "PUSH64rmm")>; +def: InstRW<[HWWriteResGroup25], (instregex "SUB64mi8")>; +def: InstRW<[HWWriteResGroup25], (instregex "SUB64mr")>; +def: InstRW<[HWWriteResGroup25], (instregex "SUB8mi")>; +def: InstRW<[HWWriteResGroup25], (instregex "SUB8mr")>; +def: InstRW<[HWWriteResGroup25], (instregex "XOR64mi8")>; +def: InstRW<[HWWriteResGroup25], (instregex "XOR64mr")>; +def: InstRW<[HWWriteResGroup25], (instregex "XOR8mi")>; +def: InstRW<[HWWriteResGroup25], (instregex "XOR8mr")>; + +def HWWriteResGroup26 : SchedWriteRes<[HWPort5]> { + let Latency = 2; let NumMicroOps = 2; - let ResourceCycles = [1, 1]; + let ResourceCycles = [2]; } - -// Notation: -// - r: register. -// - mm: 64 bit mmx register. -// - x = 128 bit xmm register. -// - (x)mm = mmx or xmm register. -// - y = 256 bit ymm register. -// - v = any vector register. -// - m = memory. - -//=== Integer Instructions ===// -//-- Move instructions --// - -// MOV. -// r16,m. -def : InstRW<[WriteALULd], (instregex "MOV16rm")>; - -// MOVSX, MOVZX. -// r,m. -def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>; - -// CMOVcc. -// r,r. -def : InstRW<[Write2P0156_Lat2], - (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>; -// r,m. -def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd], - (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>; - -// XCHG. -// r,r. -def WriteXCHG : SchedWriteRes<[HWPort0156]> { +def: InstRW<[HWWriteResGroup26], (instregex "BLENDVPDrr0")>; +def: InstRW<[HWWriteResGroup26], (instregex "BLENDVPSrr0")>; +def: InstRW<[HWWriteResGroup26], (instregex "MMX_PINSRWirri")>; +def: InstRW<[HWWriteResGroup26], (instregex "PBLENDVBrr0")>; +def: InstRW<[HWWriteResGroup26], (instregex "PINSRBrr")>; +def: InstRW<[HWWriteResGroup26], (instregex "PINSRDrr")>; +def: InstRW<[HWWriteResGroup26], (instregex "PINSRQrr")>; +def: InstRW<[HWWriteResGroup26], (instregex "PINSRWrri")>; +def: InstRW<[HWWriteResGroup26], (instregex "VBLENDVPDYrr")>; +def: InstRW<[HWWriteResGroup26], (instregex "VBLENDVPDrr")>; +def: InstRW<[HWWriteResGroup26], (instregex "VBLENDVPSYrr")>; +def: InstRW<[HWWriteResGroup26], (instregex "VBLENDVPSrr")>; +def: InstRW<[HWWriteResGroup26], (instregex "VPBLENDVBYrr")>; +def: InstRW<[HWWriteResGroup26], (instregex "VPBLENDVBrr")>; +def: InstRW<[HWWriteResGroup26], (instregex "VPINSRBrr")>; +def: InstRW<[HWWriteResGroup26], (instregex "VPINSRDrr")>; +def: InstRW<[HWWriteResGroup26], (instregex "VPINSRQrr")>; +def: InstRW<[HWWriteResGroup26], (instregex "VPINSRWrri")>; + +def HWWriteResGroup27 : SchedWriteRes<[HWPort01]> { let Latency = 2; - let ResourceCycles = [3]; -} - -def : InstRW<[WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>; - -// r,m. -def WriteXCHGrm : SchedWriteRes<[]> { - let Latency = 21; - let NumMicroOps = 8; -} -def : InstRW<[WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>; - -// XLAT. -def WriteXLAT : SchedWriteRes<[]> { - let Latency = 7; - let NumMicroOps = 3; -} -def : InstRW<[WriteXLAT], (instregex "XLAT")>; - -// PUSH. -// m. -def : InstRW<[Write2P237_P4], (instregex "PUSH(16|32)rmm")>; - -// PUSHF. -def WritePushF : SchedWriteRes<[HWPort1, HWPort4, HWPort237, HWPort06]> { - let NumMicroOps = 4; + let NumMicroOps = 2; + let ResourceCycles = [2]; } -def : InstRW<[WritePushF], (instregex "PUSHF(16|32)")>; +def: InstRW<[HWWriteResGroup27], (instregex "FDECSTP")>; -// PUSHA. -def WritePushA : SchedWriteRes<[]> { - let NumMicroOps = 19; +def HWWriteResGroup28 : SchedWriteRes<[HWPort0]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; } -def : InstRW<[WritePushA], (instregex "PUSHA(16|32)")>; - -// POP. -// m. -def : InstRW<[Write2P237_P4], (instregex "POP(16|32)rmm")>; +def: InstRW<[HWWriteResGroup28], (instregex "ROL32ri")>; +def: InstRW<[HWWriteResGroup28], (instregex "ROL64r1")>; +def: InstRW<[HWWriteResGroup28], (instregex "ROL8r1")>; +def: InstRW<[HWWriteResGroup28], (instregex "ROL8ri")>; +def: InstRW<[HWWriteResGroup28], (instregex "ROR32ri")>; +def: InstRW<[HWWriteResGroup28], (instregex "ROR64r1")>; +def: InstRW<[HWWriteResGroup28], (instregex "ROR8r1")>; +def: InstRW<[HWWriteResGroup28], (instregex "ROR8ri")>; -// POPF. -def WritePopF : SchedWriteRes<[]> { - let NumMicroOps = 9; +def HWWriteResGroup29 : SchedWriteRes<[HWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; } -def : InstRW<[WritePopF], (instregex "POPF(16|32)")>; +def: InstRW<[HWWriteResGroup29], (instregex "LFENCE")>; +def: InstRW<[HWWriteResGroup29], (instregex "MFENCE")>; +def: InstRW<[HWWriteResGroup29], (instregex "WAIT")>; +def: InstRW<[HWWriteResGroup29], (instregex "XGETBV")>; -// POPA. -def WritePopA : SchedWriteRes<[]> { - let NumMicroOps = 18; +def HWWriteResGroup30 : SchedWriteRes<[HWPort0,HWPort5]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup30], (instregex "CVTPS2PDrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "CVTSS2SDrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "EXTRACTPSrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "MMX_PEXTRWirri")>; +def: InstRW<[HWWriteResGroup30], (instregex "PEXTRBrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "PEXTRDrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "PEXTRQrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "PEXTRWri")>; +def: InstRW<[HWWriteResGroup30], (instregex "PSLLDrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "PSLLQrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "PSLLWrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "PSRADrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "PSRAWrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "PSRLDrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "PSRLQrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "PSRLWrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "PTESTrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VCVTPH2PSYrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VCVTPH2PSrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VCVTPS2PDrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VCVTSS2SDrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VEXTRACTPSrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VPEXTRBrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VPEXTRDrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VPEXTRQrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VPEXTRWri")>; +def: InstRW<[HWWriteResGroup30], (instregex "VPSRADrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VPSRAWrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VPSRLDrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VPSRLQrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VPSRLWrr")>; +def: InstRW<[HWWriteResGroup30], (instregex "VPTESTrr")>; + +def HWWriteResGroup31 : SchedWriteRes<[HWPort6,HWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; } -def : InstRW<[WritePopA], (instregex "POPA(16|32)")>; - -// LAHF SAHF. -def : InstRW<[WriteP06], (instregex "(S|L)AHF")>; +def: InstRW<[HWWriteResGroup31], (instregex "CLFLUSH")>; -// BSWAP. -// r32. -def WriteBSwap32 : SchedWriteRes<[HWPort15]>; -def : InstRW<[WriteBSwap32], (instregex "BSWAP32r")>; - -// r64. -def WriteBSwap64 : SchedWriteRes<[HWPort06, HWPort15]> { +def HWWriteResGroup32 : SchedWriteRes<[HWPort01,HWPort015]> { + let Latency = 2; let NumMicroOps = 2; + let ResourceCycles = [1,1]; } -def : InstRW<[WriteBSwap64], (instregex "BSWAP64r")>; - -// MOVBE. -// r16,m16 / r64,m64. -def : InstRW<[Write2P0156_Lat2Ld], (instregex "MOVBE(16|64)rm")>; +def: InstRW<[HWWriteResGroup32], (instregex "MMX_MOVDQ2Qrr")>; -// r32, m32. -def WriteMoveBE32rm : SchedWriteRes<[HWPort15, HWPort23]> { +def HWWriteResGroup33 : SchedWriteRes<[HWPort0,HWPort15]> { + let Latency = 2; let NumMicroOps = 2; + let ResourceCycles = [1,1]; } -def : InstRW<[WriteMoveBE32rm], (instregex "MOVBE32rm")>; +def: InstRW<[HWWriteResGroup33], (instregex "BEXTR32rr")>; +def: InstRW<[HWWriteResGroup33], (instregex "BEXTR64rr")>; +def: InstRW<[HWWriteResGroup33], (instregex "BSWAP32r")>; -// m16,r16. -def WriteMoveBE16mr : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> { +def HWWriteResGroup34 : SchedWriteRes<[HWPort0,HWPort0156]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup34], (instregex "ADC64ri8")>; +def: InstRW<[HWWriteResGroup34], (instregex "ADC64rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "ADC8ri")>; +def: InstRW<[HWWriteResGroup34], (instregex "ADC8rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVAE32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVB32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVE32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVG32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVGE32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVL32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVLE32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVNE32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVNO32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVNP32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVNS32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVO32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVP32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CMOVS32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "CWD")>; +def: InstRW<[HWWriteResGroup34], (instregex "SBB32rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "SBB64ri8")>; +def: InstRW<[HWWriteResGroup34], (instregex "SBB8ri")>; +def: InstRW<[HWWriteResGroup34], (instregex "SBB8rr")>; +def: InstRW<[HWWriteResGroup34], (instregex "SETAr")>; +def: InstRW<[HWWriteResGroup34], (instregex "SETBEr")>; + +def HWWriteResGroup35 : SchedWriteRes<[HWPort5,HWPort23]> { + let Latency = 2; let NumMicroOps = 3; -} -def : InstRW<[WriteMoveBE16mr], (instregex "MOVBE16mr")>; - -// m32,r32. -def WriteMoveBE32mr : SchedWriteRes<[HWPort15, HWPort237, HWPort4]> { + let ResourceCycles = [2,1]; +} +def: InstRW<[HWWriteResGroup35], (instregex "BLENDVPDrm0")>; +def: InstRW<[HWWriteResGroup35], (instregex "BLENDVPSrm0")>; +def: InstRW<[HWWriteResGroup35], (instregex "MMX_PACKSSDWirm")>; +def: InstRW<[HWWriteResGroup35], (instregex "MMX_PACKSSWBirm")>; +def: InstRW<[HWWriteResGroup35], (instregex "MMX_PACKUSWBirm")>; +def: InstRW<[HWWriteResGroup35], (instregex "PBLENDVBrm0")>; +def: InstRW<[HWWriteResGroup35], (instregex "VBLENDVPDYrm")>; +def: InstRW<[HWWriteResGroup35], (instregex "VBLENDVPDrm")>; +def: InstRW<[HWWriteResGroup35], (instregex "VBLENDVPSYrm")>; +def: InstRW<[HWWriteResGroup35], (instregex "VBLENDVPSrm")>; +def: InstRW<[HWWriteResGroup35], (instregex "VMASKMOVPDrm")>; +def: InstRW<[HWWriteResGroup35], (instregex "VMASKMOVPDrm")>; +def: InstRW<[HWWriteResGroup35], (instregex "VMASKMOVPSrm")>; +def: InstRW<[HWWriteResGroup35], (instregex "VMASKMOVPSrm")>; +def: InstRW<[HWWriteResGroup35], (instregex "VPBLENDVBYrm")>; +def: InstRW<[HWWriteResGroup35], (instregex "VPBLENDVBrm")>; +def: InstRW<[HWWriteResGroup35], (instregex "VPMASKMOVDYrm")>; +def: InstRW<[HWWriteResGroup35], (instregex "VPMASKMOVDrm")>; +def: InstRW<[HWWriteResGroup35], (instregex "VPMASKMOVQYrm")>; +def: InstRW<[HWWriteResGroup35], (instregex "VPMASKMOVQrm")>; + +def HWWriteResGroup36 : SchedWriteRes<[HWPort23,HWPort0156]> { + let Latency = 2; let NumMicroOps = 3; + let ResourceCycles = [1,2]; } -def : InstRW<[WriteMoveBE32mr], (instregex "MOVBE32mr")>; - -// m64,r64. -def WriteMoveBE64mr : SchedWriteRes<[HWPort06, HWPort15, HWPort237, HWPort4]> { - let NumMicroOps = 4; -} -def : InstRW<[WriteMoveBE64mr], (instregex "MOVBE64mr")>; - -//-- Arithmetic instructions --// - -// ADD SUB. -// m,r/i. -def : InstRW<[Write2P0156_2P237_P4], - (instregex "(ADD|SUB)(8|16|32|64)m(r|i)", - "(ADD|SUB)(8|16|32|64)mi8", "(ADD|SUB)64mi32")>; - -// ADC SBB. -// r,r/i. -def : InstRW<[Write2P0156_Lat2], (instregex "(ADC|SBB)(8|16|32|64)r(r|i)", - "(ADC|SBB)(16|32|64)ri8", - "(ADC|SBB)64ri32", - "(ADC|SBB)(8|16|32|64)rr_REV")>; - -// r,m. -def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd], (instregex "(ADC|SBB)(8|16|32|64)rm")>; - -// m,r/i. -def : InstRW<[Write3P0156_2P237_P4], - (instregex "(ADC|SBB)(8|16|32|64)m(r|i)", - "(ADC|SBB)(16|32|64)mi8", - "(ADC|SBB)64mi32")>; - -// INC DEC NOT NEG. -// m. -def : InstRW<[WriteP0156_2P237_P4], - (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m", - "(INC|DEC)64(16|32)m")>; - -// MUL IMUL. -// r16. -def WriteMul16 : SchedWriteRes<[HWPort1, HWPort0156]> { - let Latency = 4; - let NumMicroOps = 4; -} -def : InstRW<[WriteMul16], (instregex "IMUL16r", "MUL16r")>; - -// m16. -def WriteMul16Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> { - let Latency = 8; - let NumMicroOps = 5; -} -def : InstRW<[WriteMul16Ld], (instregex "IMUL16m", "MUL16m")>; +def: InstRW<[HWWriteResGroup36], (instregex "LEAVE64")>; +def: InstRW<[HWWriteResGroup36], (instregex "SCASB")>; +def: InstRW<[HWWriteResGroup36], (instregex "SCASL")>; +def: InstRW<[HWWriteResGroup36], (instregex "SCASQ")>; +def: InstRW<[HWWriteResGroup36], (instregex "SCASW")>; -// r32. -def WriteMul32 : SchedWriteRes<[HWPort1, HWPort0156]> { - let Latency = 4; +def HWWriteResGroup37 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> { + let Latency = 2; let NumMicroOps = 3; -} -def : InstRW<[WriteMul32], (instregex "IMUL32r", "MUL32r")>; - -// m32. -def WriteMul32Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> { - let Latency = 8; - let NumMicroOps = 4; -} -def : InstRW<[WriteMul32Ld], (instregex "IMUL32m", "MUL32m")>; - -// r64. -def WriteMul64 : SchedWriteRes<[HWPort1, HWPort6]> { - let Latency = 3; - let NumMicroOps = 2; -} -def : InstRW<[WriteMul64], (instregex "IMUL64r", "MUL64r")>; - -// m64. -def WriteMul64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> { - let Latency = 7; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup37], (instregex "PSLLDrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "PSLLQrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "PSLLWrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "PSRADrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "PSRAWrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "PSRLDrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "PSRLQrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "PSRLWrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "PTESTrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "VPSLLDri")>; +def: InstRW<[HWWriteResGroup37], (instregex "VPSLLQri")>; +def: InstRW<[HWWriteResGroup37], (instregex "VPSLLWri")>; +def: InstRW<[HWWriteResGroup37], (instregex "VPSRADrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "VPSRAWrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "VPSRLDrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "VPSRLQrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "VPSRLWrm")>; +def: InstRW<[HWWriteResGroup37], (instregex "VPTESTrm")>; + +def HWWriteResGroup38 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> { + let Latency = 2; let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; } -def : InstRW<[WriteMul64Ld], (instregex "IMUL64m", "MUL64m")>; - -// r16,r16. -def WriteMul16rri : SchedWriteRes<[HWPort1, HWPort0156]> { - let Latency = 4; - let NumMicroOps = 2; -} -def : InstRW<[WriteMul16rri], (instregex "IMUL16rri", "IMUL16rri8")>; +def: InstRW<[HWWriteResGroup38], (instregex "FLDCW16m")>; -// r16,m16. -def WriteMul16rmi : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> { - let Latency = 8; +def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort23,HWPort0156]> { + let Latency = 2; let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; } -def : InstRW<[WriteMul16rmi], (instregex "IMUL16rmi", "IMUL16rmi8")>; +def: InstRW<[HWWriteResGroup39], (instregex "LDMXCSR")>; +def: InstRW<[HWWriteResGroup39], (instregex "VLDMXCSR")>; -// MULX. -// r32,r32,r32. -def WriteMulX32 : SchedWriteRes<[HWPort1, HWPort056]> { - let Latency = 4; +def HWWriteResGroup40 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { + let Latency = 2; let NumMicroOps = 3; - let ResourceCycles = [1, 2]; + let ResourceCycles = [1,1,1]; } -def : InstRW<[WriteMulX32], (instregex "MULX32rr")>; +def: InstRW<[HWWriteResGroup40], (instregex "LRETQ")>; +def: InstRW<[HWWriteResGroup40], (instregex "RETQ")>; -// r32,r32,m32. -def WriteMulX32Ld : SchedWriteRes<[HWPort1, HWPort056, HWPort23]> { - let Latency = 8; - let NumMicroOps = 4; - let ResourceCycles = [1, 2, 1]; -} -def : InstRW<[WriteMulX32Ld], (instregex "MULX32rm")>; - -// r64,r64,r64. -def WriteMulX64 : SchedWriteRes<[HWPort1, HWPort6]> { - let Latency = 4; - let NumMicroOps = 2; -} -def : InstRW<[WriteMulX64], (instregex "MULX64rr")>; - -// r64,r64,m64. -def WriteMulX64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> { - let Latency = 8; +def HWWriteResGroup41 : SchedWriteRes<[HWPort23,HWPort0,HWPort15]> { + let Latency = 2; let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; } -def : InstRW<[WriteMulX64Ld], (instregex "MULX64rm")>; - -// DIV. -// r8. -def WriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { - let Latency = 22; - let NumMicroOps = 9; -} -def : InstRW<[WriteDiv8], (instregex "DIV8r")>; - -// r16. -def WriteDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { - let Latency = 23; - let NumMicroOps = 10; -} -def : InstRW<[WriteDiv16], (instregex "DIV16r")>; - -// r32. -def WriteDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { - let Latency = 22; - let NumMicroOps = 10; -} -def : InstRW<[WriteDiv32], (instregex "DIV32r")>; - -// r64. -def WriteDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { - let Latency = 32; - let NumMicroOps = 36; -} -def : InstRW<[WriteDiv64], (instregex "DIV64r")>; - -// IDIV. -// r8. -def WriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { - let Latency = 23; - let NumMicroOps = 9; -} -def : InstRW<[WriteIDiv8], (instregex "IDIV8r")>; - -// r16. -def WriteIDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { - let Latency = 23; - let NumMicroOps = 10; -} -def : InstRW<[WriteIDiv16], (instregex "IDIV16r")>; +def: InstRW<[HWWriteResGroup41], (instregex "BEXTR32rm")>; +def: InstRW<[HWWriteResGroup41], (instregex "BEXTR64rm")>; -// r32. -def WriteIDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { - let Latency = 22; - let NumMicroOps = 9; -} -def : InstRW<[WriteIDiv32], (instregex "IDIV32r")>; - -// r64. -def WriteIDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { - let Latency = 39; - let NumMicroOps = 59; -} -def : InstRW<[WriteIDiv64], (instregex "IDIV64r")>; - -//-- Logic instructions --// - -// AND OR XOR. -// m,r/i. -def : InstRW<[Write2P0156_2P237_P4], - (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)", - "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>; - -// SHR SHL SAR. -// m,i. -def WriteShiftRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> { +def HWWriteResGroup42 : SchedWriteRes<[HWPort23,HWPort0,HWPort0156]> { + let Latency = 2; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup42], (instregex "ADC64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "ADC8rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVAE64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVB64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVE64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVG64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVGE64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVL64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVLE64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVNE64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVNO64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVNP64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVNS64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVO64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVP64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "CMOVS64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "SBB64rm")>; +def: InstRW<[HWWriteResGroup42], (instregex "SBB8rm")>; + +def HWWriteResGroup43 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> { + let Latency = 2; let NumMicroOps = 4; - let ResourceCycles = [2, 1, 1]; + let ResourceCycles = [1,1,1,1]; } -def : InstRW<[WriteShiftRMW], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>; - -// r,cl. -def : InstRW<[Write3P06_Lat2], (instregex "S(A|H)(R|L)(8|16|32|64)rCL")>; +def: InstRW<[HWWriteResGroup43], (instregex "CALL64r")>; +def: InstRW<[HWWriteResGroup43], (instregex "SETAm")>; +def: InstRW<[HWWriteResGroup43], (instregex "SETBEm")>; -// m,cl. -def WriteShiftClLdRMW : SchedWriteRes<[HWPort06, HWPort23, HWPort4]> { - let NumMicroOps = 6; - let ResourceCycles = [3, 2, 1]; -} -def : InstRW<[WriteShiftClLdRMW], (instregex "S(A|H)(R|L)(8|16|32|64)mCL")>; - -// ROR ROL. -// r,1. -def : InstRW<[Write2P06], (instregex "RO(R|L)(8|16|32|64)r1")>; - -// m,i. -def WriteRotateRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> { +def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0]> { + let Latency = 2; let NumMicroOps = 5; - let ResourceCycles = [2, 2, 1]; -} -def : InstRW<[WriteRotateRMW], (instregex "RO(R|L)(8|16|32|64)mi")>; - -// r,cl. -def : InstRW<[Write3P06_Lat2], (instregex "RO(R|L)(8|16|32|64)rCL")>; - -// m,cl. -def WriteRotateRMWCL : SchedWriteRes<[]> { - let NumMicroOps = 6; -} -def : InstRW<[WriteRotateRMWCL], (instregex "RO(R|L)(8|16|32|64)mCL")>; - -// RCR RCL. -// r,1. -def WriteRCr1 : SchedWriteRes<[HWPort06, HWPort0156]> { + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[HWWriteResGroup44], (instregex "ROL64m1")>; +def: InstRW<[HWWriteResGroup44], (instregex "ROL64mi")>; +def: InstRW<[HWWriteResGroup44], (instregex "ROL8m1")>; +def: InstRW<[HWWriteResGroup44], (instregex "ROL8mi")>; +def: InstRW<[HWWriteResGroup44], (instregex "ROR64m1")>; +def: InstRW<[HWWriteResGroup44], (instregex "ROR64mi")>; +def: InstRW<[HWWriteResGroup44], (instregex "ROR8m1")>; +def: InstRW<[HWWriteResGroup44], (instregex "ROR8mi")>; + +def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [2, 1]; -} -def : InstRW<[WriteRCr1], (instregex "RC(R|L)(8|16|32|64)r1")>; - -// m,1. -def WriteRCm1 : SchedWriteRes<[]> { - let NumMicroOps = 6; -} -def : InstRW<[WriteRCm1], (instregex "RC(R|L)(8|16|32|64)m1")>; - -// r,i. -def WriteRCri : SchedWriteRes<[HWPort0156]> { - let Latency = 6; - let NumMicroOps = 8; -} -def : InstRW<[WriteRCri], (instregex "RC(R|L)(8|16|32|64)r(i|CL)")>; - -// m,i. -def WriteRCmi : SchedWriteRes<[]> { - let NumMicroOps = 11; -} -def : InstRW<[WriteRCmi], (instregex "RC(R|L)(8|16|32|64)m(i|CL)")>; - -// SHRD SHLD. -// r,r,i. -def WriteShDrr : SchedWriteRes<[HWPort1]> { - let Latency = 3; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; } -def : InstRW<[WriteShDrr], (instregex "SH(R|L)D(16|32|64)rri8")>; +def: InstRW<[HWWriteResGroup45], (instregex "XADD64rm")>; +def: InstRW<[HWWriteResGroup45], (instregex "XADD8rm")>; -// m,r,i. -def WriteShDmr : SchedWriteRes<[]> { +def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { + let Latency = 2; let NumMicroOps = 5; + let ResourceCycles = [1,1,1,1,1]; } -def : InstRW<[WriteShDmr], (instregex "SH(R|L)D(16|32|64)mri8")>; +def: InstRW<[HWWriteResGroup46], (instregex "CALL64m")>; +def: InstRW<[HWWriteResGroup46], (instregex "FARCALL64")>; -// r,r,cl. -def WriteShlDCL : SchedWriteRes<[HWPort0156]> { +def HWWriteResGroup47 : SchedWriteRes<[HWPort0]> { let Latency = 3; - let NumMicroOps = 4; -} -def : InstRW<[WriteShlDCL], (instregex "SHLD(16|32|64)rrCL")>; - -// r,r,cl. -def WriteShrDCL : SchedWriteRes<[HWPort0156]> { - let Latency = 4; - let NumMicroOps = 4; -} -def : InstRW<[WriteShrDCL], (instregex "SHRD(16|32|64)rrCL")>; - -// m,r,cl. -def WriteShDmrCL : SchedWriteRes<[]> { - let NumMicroOps = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; } -def : InstRW<[WriteShDmrCL], (instregex "SH(R|L)D(16|32|64)mrCL")>; - -// BT. -// r,r/i. -def : InstRW<[WriteShift], (instregex "BT(16|32|64)r(r|i8)")>; +def: InstRW<[HWWriteResGroup47], (instregex "MOVMSKPDrr")>; +def: InstRW<[HWWriteResGroup47], (instregex "MOVMSKPSrr")>; +def: InstRW<[HWWriteResGroup47], (instregex "PMOVMSKBrr")>; +def: InstRW<[HWWriteResGroup47], (instregex "VMOVMSKPDYrr")>; +def: InstRW<[HWWriteResGroup47], (instregex "VMOVMSKPDrr")>; +def: InstRW<[HWWriteResGroup47], (instregex "VMOVMSKPSrr")>; +def: InstRW<[HWWriteResGroup47], (instregex "VPMOVMSKBYrr")>; +def: InstRW<[HWWriteResGroup47], (instregex "VPMOVMSKBrr")>; -// m,r. -def WriteBTmr : SchedWriteRes<[]> { - let NumMicroOps = 10; +def HWWriteResGroup48 : SchedWriteRes<[HWPort1]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; } -def : InstRW<[WriteBTmr], (instregex "BT(16|32|64)mr")>; - -// m,i. -def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>; - -// BTR BTS BTC. -// r,r,i. -def : InstRW<[WriteShift], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>; - -// m,r. -def WriteBTRSCmr : SchedWriteRes<[]> { - let NumMicroOps = 11; +def: InstRW<[HWWriteResGroup48], (instregex "ADDPDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "ADDPSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "ADDSDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "ADDSSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "ADDSUBPDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "ADDSUBPSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "BSF32rr")>; +def: InstRW<[HWWriteResGroup48], (instregex "BSR32rr")>; +def: InstRW<[HWWriteResGroup48], (instregex "CMPPDrri")>; +def: InstRW<[HWWriteResGroup48], (instregex "CMPPSrri")>; +def: InstRW<[HWWriteResGroup48], (instregex "CMPSDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "CMPSSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "COMISDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "COMISSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "CVTDQ2PSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "CVTPS2DQrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "CVTTPS2DQrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "IMUL32rri8")>; +def: InstRW<[HWWriteResGroup48], (instregex "IMUL64rr")>; +def: InstRW<[HWWriteResGroup48], (instregex "IMUL8r")>; +def: InstRW<[HWWriteResGroup48], (instregex "LZCNT32rr")>; +def: InstRW<[HWWriteResGroup48], (instregex "MAXPDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "MAXPSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "MAXSDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "MAXSSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "MINPDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "MINPSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "MINSDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "MINSSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "MMX_CVTPI2PSirr")>; +def: InstRW<[HWWriteResGroup48], (instregex "MUL8r")>; +def: InstRW<[HWWriteResGroup48], (instregex "PDEP32rr")>; +def: InstRW<[HWWriteResGroup48], (instregex "PDEP64rr")>; +def: InstRW<[HWWriteResGroup48], (instregex "PEXT32rr")>; +def: InstRW<[HWWriteResGroup48], (instregex "PEXT64rr")>; +def: InstRW<[HWWriteResGroup48], (instregex "POPCNT32rr")>; +def: InstRW<[HWWriteResGroup48], (instregex "SHLD32rri8")>; +def: InstRW<[HWWriteResGroup48], (instregex "SHRD32rri8")>; +def: InstRW<[HWWriteResGroup48], (instregex "SUBPDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "SUBPSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "SUBSDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "SUBSSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "TZCNT32rr")>; +def: InstRW<[HWWriteResGroup48], (instregex "UCOMISDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "UCOMISSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VADDPDYrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VADDPDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VADDPSYrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VADDPSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VADDSDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VADDSSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VADDSUBPDYrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VADDSUBPDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VADDSUBPSYrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VADDSUBPSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VCMPPDYrri")>; +def: InstRW<[HWWriteResGroup48], (instregex "VCMPPDrri")>; +def: InstRW<[HWWriteResGroup48], (instregex "VCMPPSYrri")>; +def: InstRW<[HWWriteResGroup48], (instregex "VCMPPSrri")>; +def: InstRW<[HWWriteResGroup48], (instregex "VCMPSDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VCMPSSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VCOMISDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VCOMISSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VCVTDQ2PSYrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VCVTDQ2PSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VCVTPS2DQYrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VCVTPS2DQrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VCVTTPS2DQrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VMAXPDYrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VMAXPDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VMAXPSYrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VMAXPSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VMAXSDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VMAXSSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VMINPDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VMINPSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VMINSDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VMINSSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VSUBPDYrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VSUBPDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VSUBPSYrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VSUBPSrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VUCOMISDrr")>; +def: InstRW<[HWWriteResGroup48], (instregex "VUCOMISSrr")>; + +def HWWriteResGroup49 : SchedWriteRes<[HWPort5]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; } -def : InstRW<[WriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>; - -// m,i. -def : InstRW<[WriteShiftLd], (instregex "BT(R|S|C)(16|32|64)mi8")>; - -// BSF BSR. -// r,r. -def : InstRW<[WriteP1_Lat3], (instregex "BS(R|F)(16|32|64)rr")>; -// r,m. -def : InstRW<[WriteP1_Lat3Ld], (instregex "BS(R|F)(16|32|64)rm")>; - -// SETcc. -// r. -def : InstRW<[WriteShift], - (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)r")>; -// m. -def WriteSetCCm : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> { +def: InstRW<[HWWriteResGroup49], (instregex "KSHIFTRDri")>; +def: InstRW<[HWWriteResGroup49], (instregex "KSHIFTRWri")>; +def: InstRW<[HWWriteResGroup49], (instregex "VBROADCASTSDYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VBROADCASTSSrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VEXTRACTF128rr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VEXTRACTI128rr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VINSERTF128rr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VINSERTI128rr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPBROADCASTBYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPBROADCASTBrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPBROADCASTDYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPBROADCASTQYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPBROADCASTWYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPBROADCASTWrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPERM2I128rr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPERMDYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPERMQYri")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPMOVSXBDYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPMOVSXBQYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPMOVSXBWYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPMOVSXDQYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPMOVSXWDYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPMOVSXWQYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPMOVZXBDYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPMOVZXBQYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPMOVZXBWYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPMOVZXDQYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPMOVZXWDYrr")>; +def: InstRW<[HWWriteResGroup49], (instregex "VPMOVZXWQYrr")>; + +def HWWriteResGroup50 : SchedWriteRes<[HWPort1,HWPort23]> { + let Latency = 3; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup50], (instregex "ADDPDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "ADDPSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "ADDSDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "ADDSSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "ADDSUBPDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "ADDSUBPSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "BSF64rm")>; +def: InstRW<[HWWriteResGroup50], (instregex "BSR64rm")>; +def: InstRW<[HWWriteResGroup50], (instregex "CMPPDrmi")>; +def: InstRW<[HWWriteResGroup50], (instregex "CMPPSrmi")>; +def: InstRW<[HWWriteResGroup50], (instregex "CMPSSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "COMISDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "COMISSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "CVTDQ2PSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "CVTPS2DQrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "CVTTPS2DQrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "IMUL64m")>; +def: InstRW<[HWWriteResGroup50], (instregex "IMUL64rm")>; +def: InstRW<[HWWriteResGroup50], (instregex "IMUL8m")>; +def: InstRW<[HWWriteResGroup50], (instregex "LZCNT64rm")>; +def: InstRW<[HWWriteResGroup50], (instregex "MAXPDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "MAXPSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "MAXSDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "MAXSSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "MINPDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "MINPSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "MINSDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "MINSSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTPI2PSirm")>; +def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTPS2PIirm")>; +def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTTPS2PIirm")>; +def: InstRW<[HWWriteResGroup50], (instregex "MUL64m")>; +def: InstRW<[HWWriteResGroup50], (instregex "MUL8m")>; +def: InstRW<[HWWriteResGroup50], (instregex "PDEP32rm")>; +def: InstRW<[HWWriteResGroup50], (instregex "PDEP64rm")>; +def: InstRW<[HWWriteResGroup50], (instregex "PEXT32rm")>; +def: InstRW<[HWWriteResGroup50], (instregex "PEXT64rm")>; +def: InstRW<[HWWriteResGroup50], (instregex "POPCNT64rm")>; +def: InstRW<[HWWriteResGroup50], (instregex "SUBPDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "SUBPSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "SUBSDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "SUBSSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "TZCNT64rm")>; +def: InstRW<[HWWriteResGroup50], (instregex "UCOMISDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "UCOMISSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VADDPDYrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VADDPDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VADDPSYrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VADDPSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VADDSDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VADDSSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VADDSUBPDYrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VADDSUBPDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VADDSUBPSYrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VADDSUBPSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCMPPDYrmi")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCMPPDrmi")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCMPPSYrmi")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCMPPSrmi")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCMPSDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCMPSSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCOMISDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCOMISSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCVTDQ2PSYrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCVTDQ2PSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCVTPS2DQYrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCVTPS2DQrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCVTTPS2DQrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VCVTTPS2DQrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VMAXPDYrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VMAXPDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VMAXPSYrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VMAXPSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VMAXSDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VMAXSSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VMINPDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VMINPDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VMINPSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VMINPSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VMINSDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VMINSSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VSUBPDYrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VSUBPDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VSUBPSYrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VSUBPSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VSUBSDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VSUBSSrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VUCOMISDrm")>; +def: InstRW<[HWWriteResGroup50], (instregex "VUCOMISSrm")>; + +def HWWriteResGroup51 : SchedWriteRes<[HWPort5,HWPort23]> { + let Latency = 3; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup51], (instregex "VPERM2F128rm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPERM2I128rm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPERMDYrm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPERMPDYmi")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPERMPSYrm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPERMQYmi")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXBDYrm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXBQYrm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXBWYrm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXDQYrm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXWDYrm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXWQYrm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXBDYrm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXBQYrm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXBWYrm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXDQYrm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXWDYrm")>; +def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXWQYrm")>; + +def HWWriteResGroup52 : SchedWriteRes<[HWPort0156]> { + let Latency = 3; let NumMicroOps = 3; + let ResourceCycles = [3]; } -def : InstRW<[WriteSetCCm], - (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)m")>; +def: InstRW<[HWWriteResGroup52], (instregex "XADD32rr")>; +def: InstRW<[HWWriteResGroup52], (instregex "XADD8rr")>; +def: InstRW<[HWWriteResGroup52], (instregex "XCHG8rr")>; -// CLD STD. -def WriteCldStd : SchedWriteRes<[HWPort15, HWPort6]> { +def HWWriteResGroup53 : SchedWriteRes<[HWPort0,HWPort5]> { + let Latency = 3; let NumMicroOps = 3; + let ResourceCycles = [2,1]; } -def : InstRW<[WriteCldStd], (instregex "STD", "CLD")>; - -// LZCNT TZCNT. -// r,r. -def : InstRW<[WriteP1_Lat3], (instregex "(L|TZCNT)(16|32|64)rr")>; -// r,m. -def : InstRW<[WriteP1_Lat3Ld], (instregex "(L|TZCNT)(16|32|64)rm")>; - -// ANDN. -// r,r. -def : InstRW<[WriteP15], (instregex "ANDN(32|64)rr")>; -// r,m. -def : InstRW<[WriteP15Ld], (instregex "ANDN(32|64)rm")>; - -// BLSI BLSMSK BLSR. -// r,r. -def : InstRW<[WriteP15], (instregex "BLS(I|MSK|R)(32|64)rr")>; -// r,m. -def : InstRW<[WriteP15Ld], (instregex "BLS(I|MSK|R)(32|64)rm")>; - -// BEXTR. -// r,r,r. -def : InstRW<[Write2P0156_Lat2], (instregex "BEXTR(32|64)rr")>; -// r,m,r. -def : InstRW<[Write2P0156_Lat2Ld], (instregex "BEXTR(32|64)rm")>; - -// BZHI. -// r,r,r. -def : InstRW<[WriteP15], (instregex "BZHI(32|64)rr")>; -// r,m,r. -def : InstRW<[WriteP15Ld], (instregex "BZHI(32|64)rm")>; - -// PDEP PEXT. -// r,r,r. -def : InstRW<[WriteP1_Lat3], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>; -// r,m,r. -def : InstRW<[WriteP1_Lat3Ld], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>; - -//-- Control transfer instructions --// - -// J(E|R)CXZ. -def WriteJCXZ : SchedWriteRes<[HWPort0156, HWPort6]> { - let NumMicroOps = 2; -} -def : InstRW<[WriteJCXZ], (instregex "JCXZ", "JECXZ_(32|64)", "JRCXZ")>; +def: InstRW<[HWWriteResGroup53], (instregex "VPSLLVDYrr")>; +def: InstRW<[HWWriteResGroup53], (instregex "VPSLLVDrr")>; +def: InstRW<[HWWriteResGroup53], (instregex "VPSRAVDYrr")>; +def: InstRW<[HWWriteResGroup53], (instregex "VPSRAVDrr")>; +def: InstRW<[HWWriteResGroup53], (instregex "VPSRLVDYrr")>; +def: InstRW<[HWWriteResGroup53], (instregex "VPSRLVDrr")>; -// LOOP. -def WriteLOOP : SchedWriteRes<[]> { - let NumMicroOps = 7; +def HWWriteResGroup54 : SchedWriteRes<[HWPort5,HWPort15]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[HWWriteResGroup54], (instregex "MMX_PHADDSWrr64")>; +def: InstRW<[HWWriteResGroup54], (instregex "MMX_PHADDWrr64")>; +def: InstRW<[HWWriteResGroup54], (instregex "MMX_PHADDrr64")>; +def: InstRW<[HWWriteResGroup54], (instregex "MMX_PHSUBDrr64")>; +def: InstRW<[HWWriteResGroup54], (instregex "MMX_PHSUBSWrr64")>; +def: InstRW<[HWWriteResGroup54], (instregex "MMX_PHSUBWrr64")>; +def: InstRW<[HWWriteResGroup54], (instregex "PHADDDrr")>; +def: InstRW<[HWWriteResGroup54], (instregex "PHADDSWrr128")>; +def: InstRW<[HWWriteResGroup54], (instregex "PHADDWrr")>; +def: InstRW<[HWWriteResGroup54], (instregex "PHSUBDrr")>; +def: InstRW<[HWWriteResGroup54], (instregex "PHSUBSWrr128")>; +def: InstRW<[HWWriteResGroup54], (instregex "PHSUBWrr")>; +def: InstRW<[HWWriteResGroup54], (instregex "VPHADDDYrr")>; +def: InstRW<[HWWriteResGroup54], (instregex "VPHADDDrr")>; +def: InstRW<[HWWriteResGroup54], (instregex "VPHADDSWrr128")>; +def: InstRW<[HWWriteResGroup54], (instregex "VPHADDSWrr256")>; +def: InstRW<[HWWriteResGroup54], (instregex "VPHADDWYrr")>; +def: InstRW<[HWWriteResGroup54], (instregex "VPHADDWrr")>; +def: InstRW<[HWWriteResGroup54], (instregex "VPHSUBDYrr")>; +def: InstRW<[HWWriteResGroup54], (instregex "VPHSUBDrr")>; +def: InstRW<[HWWriteResGroup54], (instregex "VPHSUBSWrr128")>; +def: InstRW<[HWWriteResGroup54], (instregex "VPHSUBSWrr256")>; +def: InstRW<[HWWriteResGroup54], (instregex "VPHSUBWYrr")>; +def: InstRW<[HWWriteResGroup54], (instregex "VPHSUBWrr")>; + +def HWWriteResGroup55 : SchedWriteRes<[HWPort5,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; } -def : InstRW<[WriteLOOP], (instregex "LOOP")>; +def: InstRW<[HWWriteResGroup55], (instregex "MMX_PACKSSDWirr")>; +def: InstRW<[HWWriteResGroup55], (instregex "MMX_PACKSSWBirr")>; +def: InstRW<[HWWriteResGroup55], (instregex "MMX_PACKUSWBirr")>; -// LOOP(N)E -def WriteLOOPE : SchedWriteRes<[]> { - let NumMicroOps = 11; +def HWWriteResGroup56 : SchedWriteRes<[HWPort6,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; } -def : InstRW<[WriteLOOPE], (instregex "LOOPE", "LOOPNE")>; +def: InstRW<[HWWriteResGroup56], (instregex "CLD")>; -// CALL. -// r. -def WriteCALLr : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> { +def HWWriteResGroup57 : SchedWriteRes<[HWPort0,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[HWWriteResGroup57], (instregex "CMOVA32rr")>; +def: InstRW<[HWWriteResGroup57], (instregex "CMOVBE32rr")>; +def: InstRW<[HWWriteResGroup57], (instregex "RCL32ri")>; +def: InstRW<[HWWriteResGroup57], (instregex "RCL64r1")>; +def: InstRW<[HWWriteResGroup57], (instregex "RCL8r1")>; +def: InstRW<[HWWriteResGroup57], (instregex "RCL8ri")>; +def: InstRW<[HWWriteResGroup57], (instregex "RCR32ri")>; +def: InstRW<[HWWriteResGroup57], (instregex "RCR64r1")>; +def: InstRW<[HWWriteResGroup57], (instregex "RCR8r1")>; +def: InstRW<[HWWriteResGroup57], (instregex "RCR8ri")>; +def: InstRW<[HWWriteResGroup57], (instregex "SHL64rCL")>; +def: InstRW<[HWWriteResGroup57], (instregex "SHL8rCL")>; + +def HWWriteResGroup58 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> { + let Latency = 3; let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; } -def : InstRW<[WriteCALLr], (instregex "CALL(16|32)r")>; +def: InstRW<[HWWriteResGroup58], (instregex "FNSTSWm")>; -// m. -def WriteCALLm : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> { +def HWWriteResGroup59 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> { + let Latency = 3; let NumMicroOps = 4; - let ResourceCycles = [2, 1, 1]; -} -def : InstRW<[WriteCALLm], (instregex "CALL(16|32)m")>; - -// RET. -def WriteRET : SchedWriteRes<[HWPort237, HWPort6]> { - let NumMicroOps = 2; + let ResourceCycles = [2,1,1]; } -def : InstRW<[WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)")>; +def: InstRW<[HWWriteResGroup59], (instregex "VPSLLVDYrm")>; +def: InstRW<[HWWriteResGroup59], (instregex "VPSLLVDrm")>; +def: InstRW<[HWWriteResGroup59], (instregex "VPSRAVDYrm")>; +def: InstRW<[HWWriteResGroup59], (instregex "VPSRAVDrm")>; +def: InstRW<[HWWriteResGroup59], (instregex "VPSRLVDYrm")>; +def: InstRW<[HWWriteResGroup59], (instregex "VPSRLVDrm")>; -// i. -def WriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> { +def HWWriteResGroup60 : SchedWriteRes<[HWPort5,HWPort23,HWPort15]> { + let Latency = 3; let NumMicroOps = 4; - let ResourceCycles = [1, 2, 1]; -} -def : InstRW<[WriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>; - -// BOUND. -// r,m. -def WriteBOUND : SchedWriteRes<[]> { - let NumMicroOps = 15; -} -def : InstRW<[WriteBOUND], (instregex "BOUNDS(16|32)rm")>; - -// INTO. -def WriteINTO : SchedWriteRes<[]> { + let ResourceCycles = [2,1,1]; +} +def: InstRW<[HWWriteResGroup60], (instregex "MMX_PHADDSWrm64")>; +def: InstRW<[HWWriteResGroup60], (instregex "MMX_PHADDWrm64")>; +def: InstRW<[HWWriteResGroup60], (instregex "MMX_PHADDrm64")>; +def: InstRW<[HWWriteResGroup60], (instregex "MMX_PHSUBDrm64")>; +def: InstRW<[HWWriteResGroup60], (instregex "MMX_PHSUBSWrm64")>; +def: InstRW<[HWWriteResGroup60], (instregex "MMX_PHSUBWrm64")>; +def: InstRW<[HWWriteResGroup60], (instregex "PHADDDrm")>; +def: InstRW<[HWWriteResGroup60], (instregex "PHADDSWrm128")>; +def: InstRW<[HWWriteResGroup60], (instregex "PHADDWrm")>; +def: InstRW<[HWWriteResGroup60], (instregex "PHSUBDrm")>; +def: InstRW<[HWWriteResGroup60], (instregex "PHSUBSWrm128")>; +def: InstRW<[HWWriteResGroup60], (instregex "PHSUBWrm")>; +def: InstRW<[HWWriteResGroup60], (instregex "VPHADDDYrm")>; +def: InstRW<[HWWriteResGroup60], (instregex "VPHADDDrm")>; +def: InstRW<[HWWriteResGroup60], (instregex "VPHADDSWrm128")>; +def: InstRW<[HWWriteResGroup60], (instregex "VPHADDSWrm256")>; +def: InstRW<[HWWriteResGroup60], (instregex "VPHADDWYrm")>; +def: InstRW<[HWWriteResGroup60], (instregex "VPHADDWrm")>; +def: InstRW<[HWWriteResGroup60], (instregex "VPHSUBDYrm")>; +def: InstRW<[HWWriteResGroup60], (instregex "VPHSUBDrm")>; +def: InstRW<[HWWriteResGroup60], (instregex "VPHSUBSWrm128")>; +def: InstRW<[HWWriteResGroup60], (instregex "VPHSUBSWrm256")>; +def: InstRW<[HWWriteResGroup60], (instregex "VPHSUBWYrm")>; +def: InstRW<[HWWriteResGroup60], (instregex "VPHSUBWrm")>; + +def HWWriteResGroup61 : SchedWriteRes<[HWPort23,HWPort0,HWPort0156]> { + let Latency = 3; let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; } -def : InstRW<[WriteINTO], (instregex "INTO")>; - -//-- String instructions --// - -// LODSB/W. -def : InstRW<[Write2P0156_P23], (instregex "LODS(B|W)")>; - -// LODSD/Q. -def : InstRW<[WriteP0156_P23], (instregex "LODS(L|Q)")>; - -// STOS. -def WriteSTOS : SchedWriteRes<[HWPort23, HWPort0156, HWPort4]> { - let NumMicroOps = 3; -} -def : InstRW<[WriteSTOS], (instregex "STOS(B|L|Q|W)")>; +def: InstRW<[HWWriteResGroup61], (instregex "CMOVA64rm")>; +def: InstRW<[HWWriteResGroup61], (instregex "CMOVBE64rm")>; -// MOVS. -def WriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> { - let Latency = 4; - let NumMicroOps = 5; - let ResourceCycles = [2, 1, 2]; -} -def : InstRW<[WriteMOVS], (instregex "MOVS(B|L|Q|W)")>; - -// SCAS. -def : InstRW<[Write2P0156_P23], (instregex "SCAS(B|W|L|Q)")>; - -// CMPS. -def WriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> { - let Latency = 4; - let NumMicroOps = 5; - let ResourceCycles = [2, 3]; -} -def : InstRW<[WriteCMPS], (instregex "CMPS(B|L|Q|W)")>; - -//-- Synchronization instructions --// - -// XADD. -def WriteXADD : SchedWriteRes<[]> { +def HWWriteResGroup62 : SchedWriteRes<[HWPort23,HWPort237,HWPort0,HWPort0156]> { + let Latency = 3; let NumMicroOps = 5; -} -def : InstRW<[WriteXADD], (instregex "XADD(8|16|32|64)rm")>; - -// CMPXCHG. -def WriteCMPXCHG : SchedWriteRes<[]> { + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[HWWriteResGroup62], (instregex "RCL64m1")>; +def: InstRW<[HWWriteResGroup62], (instregex "RCL64mi")>; +def: InstRW<[HWWriteResGroup62], (instregex "RCL8m1")>; +def: InstRW<[HWWriteResGroup62], (instregex "RCL8mi")>; +def: InstRW<[HWWriteResGroup62], (instregex "RCR64m1")>; +def: InstRW<[HWWriteResGroup62], (instregex "RCR64mi")>; +def: InstRW<[HWWriteResGroup62], (instregex "RCR8m1")>; +def: InstRW<[HWWriteResGroup62], (instregex "RCR8mi")>; + +def HWWriteResGroup63 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { + let Latency = 3; let NumMicroOps = 6; -} -def : InstRW<[WriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>; - -// CMPXCHG8B. -def WriteCMPXCHG8B : SchedWriteRes<[]> { - let NumMicroOps = 15; -} -def : InstRW<[WriteCMPXCHG8B], (instregex "CMPXCHG8B")>; - -// CMPXCHG16B. -def WriteCMPXCHG16B : SchedWriteRes<[]> { - let NumMicroOps = 22; -} -def : InstRW<[WriteCMPXCHG16B], (instregex "CMPXCHG16B")>; - -//-- Other --// - -// PAUSE. -def WritePAUSE : SchedWriteRes<[HWPort05, HWPort6]> { - let NumMicroOps = 5; - let ResourceCycles = [1, 3]; -} -def : InstRW<[WritePAUSE], (instregex "PAUSE")>; - -// LEAVE. -def : InstRW<[Write2P0156_P23], (instregex "LEAVE")>; - -// XGETBV. -def WriteXGETBV : SchedWriteRes<[]> { - let NumMicroOps = 8; -} -def : InstRW<[WriteXGETBV], (instregex "XGETBV")>; - -// RDTSC. -def WriteRDTSC : SchedWriteRes<[]> { - let NumMicroOps = 15; -} -def : InstRW<[WriteRDTSC], (instregex "RDTSC")>; - -// RDPMC. -def WriteRDPMC : SchedWriteRes<[]> { - let NumMicroOps = 34; -} -def : InstRW<[WriteRDPMC], (instregex "RDPMC")>; - -// RDRAND. -def WriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> { - let NumMicroOps = 17; - let ResourceCycles = [1, 16]; -} -def : InstRW<[WriteRDRAND], (instregex "RDRAND(16|32|64)r")>; - -//=== Floating Point x87 Instructions ===// -//-- Move instructions --// - -// FLD. -// m80. -def : InstRW<[WriteP01], (instregex "LD_Frr")>; - -def WriteLD_F80m : SchedWriteRes<[HWPort01, HWPort23]> { + let ResourceCycles = [1,1,1,3]; +} +def: InstRW<[HWWriteResGroup63], (instregex "ADC64mi8")>; +def: InstRW<[HWWriteResGroup63], (instregex "ADC8mi")>; +def: InstRW<[HWWriteResGroup63], (instregex "ADD8mi")>; +def: InstRW<[HWWriteResGroup63], (instregex "AND8mi")>; +def: InstRW<[HWWriteResGroup63], (instregex "OR8mi")>; +def: InstRW<[HWWriteResGroup63], (instregex "SUB8mi")>; +def: InstRW<[HWWriteResGroup63], (instregex "XCHG64rm")>; +def: InstRW<[HWWriteResGroup63], (instregex "XCHG8rm")>; +def: InstRW<[HWWriteResGroup63], (instregex "XOR8mi")>; + +def HWWriteResGroup64 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0,HWPort0156]> { + let Latency = 3; + let NumMicroOps = 6; + let ResourceCycles = [1,1,1,2,1]; +} +def: InstRW<[HWWriteResGroup64], (instregex "ADC64mr")>; +def: InstRW<[HWWriteResGroup64], (instregex "ADC8mr")>; +def: InstRW<[HWWriteResGroup64], (instregex "CMPXCHG64rm")>; +def: InstRW<[HWWriteResGroup64], (instregex "CMPXCHG8rm")>; +def: InstRW<[HWWriteResGroup64], (instregex "SBB64mi8")>; +def: InstRW<[HWWriteResGroup64], (instregex "SBB64mr")>; +def: InstRW<[HWWriteResGroup64], (instregex "SBB8mi")>; +def: InstRW<[HWWriteResGroup64], (instregex "SBB8mr")>; +def: InstRW<[HWWriteResGroup64], (instregex "SHL64mCL")>; +def: InstRW<[HWWriteResGroup64], (instregex "SHL8mCL")>; + +def HWWriteResGroup65 : SchedWriteRes<[HWPort0,HWPort1]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup65], (instregex "CVTSD2SI64rr")>; +def: InstRW<[HWWriteResGroup65], (instregex "CVTSD2SIrr")>; +def: InstRW<[HWWriteResGroup65], (instregex "CVTSS2SI64rr")>; +def: InstRW<[HWWriteResGroup65], (instregex "CVTSS2SIrr")>; +def: InstRW<[HWWriteResGroup65], (instregex "CVTTSD2SI64rr")>; +def: InstRW<[HWWriteResGroup65], (instregex "CVTTSD2SIrr")>; +def: InstRW<[HWWriteResGroup65], (instregex "CVTTSS2SI64rr")>; +def: InstRW<[HWWriteResGroup65], (instregex "CVTTSS2SIrr")>; +def: InstRW<[HWWriteResGroup65], (instregex "VCVTSD2SI64rr")>; +def: InstRW<[HWWriteResGroup65], (instregex "VCVTSS2SI64rr")>; +def: InstRW<[HWWriteResGroup65], (instregex "VCVTSS2SIrr")>; +def: InstRW<[HWWriteResGroup65], (instregex "VCVTTSD2SI64rr")>; +def: InstRW<[HWWriteResGroup65], (instregex "VCVTTSD2SIrr")>; +def: InstRW<[HWWriteResGroup65], (instregex "VCVTTSS2SI64rr")>; +def: InstRW<[HWWriteResGroup65], (instregex "VCVTTSS2SIrr")>; + +def HWWriteResGroup66 : SchedWriteRes<[HWPort0,HWPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup66], (instregex "VCVTPS2PDYrr")>; +def: InstRW<[HWWriteResGroup66], (instregex "VPSLLDrr")>; +def: InstRW<[HWWriteResGroup66], (instregex "VPSLLQrr")>; +def: InstRW<[HWWriteResGroup66], (instregex "VPSLLWrr")>; +def: InstRW<[HWWriteResGroup66], (instregex "VPSRADYrr")>; +def: InstRW<[HWWriteResGroup66], (instregex "VPSRAWYrr")>; +def: InstRW<[HWWriteResGroup66], (instregex "VPSRLDYrr")>; +def: InstRW<[HWWriteResGroup66], (instregex "VPSRLQYrr")>; +def: InstRW<[HWWriteResGroup66], (instregex "VPSRLWYrr")>; +def: InstRW<[HWWriteResGroup66], (instregex "VPTESTYrr")>; + +def HWWriteResGroup67 : SchedWriteRes<[HWPort1,HWPort5]> { let Latency = 4; - let NumMicroOps = 4; - let ResourceCycles = [2, 2]; -} -def : InstRW<[WriteLD_F80m], (instregex "LD_F80m")>; - -// FBLD. -// m80. -def WriteFBLD : SchedWriteRes<[]> { - let Latency = 47; - let NumMicroOps = 43; -} -def : InstRW<[WriteFBLD], (instregex "FBLDm")>; - -// FST(P). -// r. -def : InstRW<[WriteP01], (instregex "ST_(F|FP)rr")>; - -// m80. -def WriteST_FP80m : SchedWriteRes<[HWPort0156, HWPort23, HWPort4]> { - let NumMicroOps = 7; - let ResourceCycles = [3, 2, 2]; -} -def : InstRW<[WriteST_FP80m], (instregex "ST_FP80m")>; - -// FBSTP. -// m80. -def WriteFBSTP : SchedWriteRes<[]> { - let NumMicroOps = 226; -} -def : InstRW<[WriteFBSTP], (instregex "FBSTPm")>; - -// FXCHG. -def : InstRW<[WriteNop], (instregex "XCH_F")>; - -// FILD. -def WriteFILD : SchedWriteRes<[HWPort01, HWPort23]> { - let Latency = 6; let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup67], (instregex "CVTDQ2PDrr")>; +def: InstRW<[HWWriteResGroup67], (instregex "CVTPD2DQrr")>; +def: InstRW<[HWWriteResGroup67], (instregex "CVTPD2PSrr")>; +def: InstRW<[HWWriteResGroup67], (instregex "CVTSD2SSrr")>; +def: InstRW<[HWWriteResGroup67], (instregex "CVTSI2SD64rr")>; +def: InstRW<[HWWriteResGroup67], (instregex "CVTSI2SDrr")>; +def: InstRW<[HWWriteResGroup67], (instregex "CVTSI2SSrr")>; +def: InstRW<[HWWriteResGroup67], (instregex "CVTTPD2DQrr")>; +def: InstRW<[HWWriteResGroup67], (instregex "MMX_CVTPD2PIirr")>; +def: InstRW<[HWWriteResGroup67], (instregex "MMX_CVTPI2PDirr")>; +def: InstRW<[HWWriteResGroup67], (instregex "MMX_CVTPS2PIirr")>; +def: InstRW<[HWWriteResGroup67], (instregex "MMX_CVTTPD2PIirr")>; +def: InstRW<[HWWriteResGroup67], (instregex "MMX_CVTTPS2PIirr")>; +def: InstRW<[HWWriteResGroup67], (instregex "VCVTDQ2PDrr")>; +def: InstRW<[HWWriteResGroup67], (instregex "VCVTPD2DQrr")>; +def: InstRW<[HWWriteResGroup67], (instregex "VCVTPD2PSrr")>; +def: InstRW<[HWWriteResGroup67], (instregex "VCVTPS2PHrr")>; +def: InstRW<[HWWriteResGroup67], (instregex "VCVTSI2SD64rr")>; +def: InstRW<[HWWriteResGroup67], (instregex "VCVTSI2SDrr")>; +def: InstRW<[HWWriteResGroup67], (instregex "VCVTSI2SSrr")>; +def: InstRW<[HWWriteResGroup67], (instregex "VCVTTPD2DQrr")>; + +def HWWriteResGroup68 : SchedWriteRes<[HWPort1,HWPort6]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; } -def : InstRW<[WriteFILD], (instregex "ILD_F(16|32|64)m")>; +def: InstRW<[HWWriteResGroup68], (instregex "IMUL64r")>; +def: InstRW<[HWWriteResGroup68], (instregex "MUL64r")>; +def: InstRW<[HWWriteResGroup68], (instregex "MULX64rr")>; -// FIST(P) FISTTP. -def WriteFIST : SchedWriteRes<[HWPort1, HWPort23, HWPort4]> { - let Latency = 7; +def HWWriteResGroup69 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { + let Latency = 4; let NumMicroOps = 3; -} -def : InstRW<[WriteFIST], (instregex "IST_(F|FP)(16|32)m")>; - -// FLDZ. -def : InstRW<[WriteP01], (instregex "LD_F0")>; - -// FLD1. -def : InstRW<[Write2P01], (instregex "LD_F1")>; - -// FLDPI FLDL2E etc. -def : InstRW<[Write2P01], (instregex "FLDPI", "FLDL2(T|E)" "FLDL(G|N)2")>; - -// FCMOVcc. -def WriteFCMOVcc : SchedWriteRes<[HWPort0, HWPort5]> { - let Latency = 2; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup69], (instregex "CVTSD2SI64rm")>; +def: InstRW<[HWWriteResGroup69], (instregex "CVTSD2SIrm")>; +def: InstRW<[HWWriteResGroup69], (instregex "CVTSS2SI64rm")>; +def: InstRW<[HWWriteResGroup69], (instregex "CVTSS2SIrm")>; +def: InstRW<[HWWriteResGroup69], (instregex "CVTTSD2SI64rm")>; +def: InstRW<[HWWriteResGroup69], (instregex "CVTTSD2SIrm")>; +def: InstRW<[HWWriteResGroup69], (instregex "CVTTSS2SIrm")>; +def: InstRW<[HWWriteResGroup69], (instregex "VCVTSD2SI64rm")>; +def: InstRW<[HWWriteResGroup69], (instregex "VCVTSD2SI64rr")>; +def: InstRW<[HWWriteResGroup69], (instregex "VCVTSS2SI64rm")>; +def: InstRW<[HWWriteResGroup69], (instregex "VCVTSS2SIrm")>; +def: InstRW<[HWWriteResGroup69], (instregex "VCVTTSD2SI64rm")>; +def: InstRW<[HWWriteResGroup69], (instregex "VCVTTSD2SI64rr")>; +def: InstRW<[HWWriteResGroup69], (instregex "VCVTTSS2SI64rm")>; +def: InstRW<[HWWriteResGroup69], (instregex "VCVTTSS2SIrm")>; + +def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> { + let Latency = 4; let NumMicroOps = 3; - let ResourceCycles = [2, 1]; + let ResourceCycles = [1,1,1]; } -def : InstRW<[WriteFCMOVcc], (instregex "CMOV(B|BE|P|NB|NBE|NE|NP)_F")>; +def: InstRW<[HWWriteResGroup70], (instregex "VCVTPS2PDYrm")>; +def: InstRW<[HWWriteResGroup70], (instregex "VPTESTYrm")>; -// FNSTSW. -// AX. -def WriteFNSTSW : SchedWriteRes<[HWPort0, HWPort0156]> { - let NumMicroOps = 2; -} -def : InstRW<[WriteFNSTSW], (instregex "FNSTSW16r")>; - -// m16. -def WriteFNSTSWm : SchedWriteRes<[HWPort0, HWPort4, HWPort237]> { - let Latency = 6; +def HWWriteResGroup71 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { + let Latency = 4; let NumMicroOps = 3; -} -def : InstRW<[WriteFNSTSWm], (instregex "FNSTSWm")>; - -// FLDCW. -def WriteFLDCW : SchedWriteRes<[HWPort01, HWPort23, HWPort6]> { - let Latency = 7; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[HWWriteResGroup71], (instregex "CVTDQ2PDrm")>; +def: InstRW<[HWWriteResGroup71], (instregex "CVTPD2DQrm")>; +def: InstRW<[HWWriteResGroup71], (instregex "CVTPD2PSrm")>; +def: InstRW<[HWWriteResGroup71], (instregex "CVTSD2SSrm")>; +def: InstRW<[HWWriteResGroup71], (instregex "CVTTPD2DQrm")>; +def: InstRW<[HWWriteResGroup71], (instregex "MMX_CVTPD2PIirm")>; +def: InstRW<[HWWriteResGroup71], (instregex "MMX_CVTPI2PDirm")>; +def: InstRW<[HWWriteResGroup71], (instregex "MMX_CVTTPD2PIirm")>; +def: InstRW<[HWWriteResGroup71], (instregex "VCVTDQ2PDrm")>; +def: InstRW<[HWWriteResGroup71], (instregex "VCVTSD2SSrm")>; + +def HWWriteResGroup72 : SchedWriteRes<[HWPort1,HWPort6,HWPort23]> { + let Latency = 4; let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; } -def : InstRW<[WriteFLDCW], (instregex "FLDCW16m")>; +def: InstRW<[HWWriteResGroup72], (instregex "MULX64rm")>; -// FNSTCW. -def WriteFNSTCW : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> { +def HWWriteResGroup73 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> { + let Latency = 4; let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; } -def : InstRW<[WriteFNSTCW], (instregex "FNSTCW16m")>; - -// FINCSTP FDECSTP. -def : InstRW<[WriteP01], (instregex "FINCSTP", "FDECSTP")>; - -// FFREE. -def : InstRW<[WriteP01], (instregex "FFREE")>; - -// FNSAVE. -def WriteFNSAVE : SchedWriteRes<[]> { - let NumMicroOps = 147; -} -def : InstRW<[WriteFNSAVE], (instregex "FSAVEm")>; - -// FRSTOR. -def WriteFRSTOR : SchedWriteRes<[]> { - let NumMicroOps = 90; -} -def : InstRW<[WriteFRSTOR], (instregex "FRSTORm")>; - -//-- Arithmetic instructions --// - -// FABS. -def : InstRW<[WriteP0], (instregex "ABS_F")>; - -// FCHS. -def : InstRW<[WriteP0], (instregex "CHS_F")>; - -// FCOM(P) FUCOM(P). -// r. -def : InstRW<[WriteP1], (instregex "COM_FST0r", "COMP_FST0r", "UCOM_Fr", - "UCOM_FPr")>; -// m. -def : InstRW<[WriteP1_P23], (instregex "FCOM(32|64)m", "FCOMP(32|64)m")>; - -// FCOMPP FUCOMPP. -// r. -def : InstRW<[Write2P01], (instregex "FCOMPP", "UCOM_FPPr")>; - -// FCOMI(P) FUCOMI(P). -// m. -def : InstRW<[Write3P01], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr", - "UCOM_FIPr")>; - -// FICOM(P). -def : InstRW<[Write2P1_P23], (instregex "FICOM(16|32)m", "FICOMP(16|32)m")>; - -// FTST. -def : InstRW<[WriteP1], (instregex "TST_F")>; - -// FXAM. -def : InstRW<[Write2P1], (instregex "FXAM")>; - -// FPREM. -def WriteFPREM : SchedWriteRes<[]> { - let Latency = 19; - let NumMicroOps = 28; -} -def : InstRW<[WriteFPREM], (instregex "FPREM")>; - -// FPREM1. -def WriteFPREM1 : SchedWriteRes<[]> { - let Latency = 27; - let NumMicroOps = 41; -} -def : InstRW<[WriteFPREM1], (instregex "FPREM1")>; - -// FRNDINT. -def WriteFRNDINT : SchedWriteRes<[]> { - let Latency = 11; - let NumMicroOps = 17; -} -def : InstRW<[WriteFRNDINT], (instregex "FRNDINT")>; - -//-- Math instructions --// - -// FSCALE. -def WriteFSCALE : SchedWriteRes<[]> { - let Latency = 75; // 49-125 - let NumMicroOps = 50; // 25-75 -} -def : InstRW<[WriteFSCALE], (instregex "FSCALE")>; - -// FXTRACT. -def WriteFXTRACT : SchedWriteRes<[]> { - let Latency = 15; - let NumMicroOps = 17; -} -def : InstRW<[WriteFXTRACT], (instregex "FXTRACT")>; - -//-- Other instructions --// - -// FNOP. -def : InstRW<[WriteP01], (instregex "FNOP")>; - -// WAIT. -def : InstRW<[Write2P01], (instregex "WAIT")>; - -// FNCLEX. -def : InstRW<[Write5P0156], (instregex "FNCLEX")>; - -// FNINIT. -def WriteFNINIT : SchedWriteRes<[]> { - let NumMicroOps = 26; -} -def : InstRW<[WriteFNINIT], (instregex "FNINIT")>; - -//=== Integer MMX and XMM Instructions ===// -//-- Move instructions --// - -// MOVD. -// r32/64 <- (x)mm. -def : InstRW<[WriteP0], (instregex "MMX_MOVD64grr", "MMX_MOVD64from64rr", - "VMOVPDI2DIrr", "MOVPDI2DIrr")>; - -// (x)mm <- r32/64. -def : InstRW<[WriteP5], (instregex "MMX_MOVD64rr", "MMX_MOVD64to64rr", - "VMOVDI2PDIrr", "MOVDI2PDIrr")>; - -// MOVQ. -// r64 <- (x)mm. -def : InstRW<[WriteP0], (instregex "VMOVPQIto64rr")>; - -// (x)mm <- r64. -def : InstRW<[WriteP5], (instregex "VMOV64toPQIrr", "VMOVZQI2PQIrr")>; - -// (x)mm <- (x)mm. -def : InstRW<[WriteP015], (instregex "MMX_MOVQ64rr")>; - -// (V)MOVDQA/U. -// x <- x. -def : InstRW<[WriteP015], (instregex "MOVDQ(A|U)rr", "VMOVDQ(A|U)rr", - "MOVDQ(A|U)rr_REV", "VMOVDQ(A|U)rr_REV", - "VMOVDQ(A|U)Yrr", "VMOVDQ(A|U)Yrr_REV")>; - -// MOVDQ2Q. -def : InstRW<[WriteP01_P5], (instregex "MMX_MOVDQ2Qrr")>; - -// MOVQ2DQ. -def : InstRW<[WriteP015], (instregex "MMX_MOVQ2DQrr")>; - +def: InstRW<[HWWriteResGroup73], (instregex "VPBROADCASTBYrm")>; +def: InstRW<[HWWriteResGroup73], (instregex "VPBROADCASTBrm")>; +def: InstRW<[HWWriteResGroup73], (instregex "VPBROADCASTWYrm")>; +def: InstRW<[HWWriteResGroup73], (instregex "VPBROADCASTWrm")>; -// PACKSSWB/DW. -// mm <- mm. -def WriteMMXPACKSSrr : SchedWriteRes<[HWPort5]> { - let Latency = 2; - let NumMicroOps = 3; - let ResourceCycles = [3]; +def HWWriteResGroup74 : SchedWriteRes<[HWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [4]; } -def : InstRW<[WriteMMXPACKSSrr], (instregex "MMX_PACKSSDWirr", - "MMX_PACKSSWBirr", "MMX_PACKUSWBirr")>; +def: InstRW<[HWWriteResGroup74], (instregex "FNCLEX")>; -// mm <- m64. -def WriteMMXPACKSSrm : SchedWriteRes<[HWPort23, HWPort5]> { +def HWWriteResGroup75 : SchedWriteRes<[HWPort015,HWPort0156]> { let Latency = 4; - let NumMicroOps = 3; - let ResourceCycles = [1, 3]; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; } -def : InstRW<[WriteMMXPACKSSrm], (instregex "MMX_PACKSSDWirm", - "MMX_PACKSSWBirm", "MMX_PACKUSWBirm")>; +def: InstRW<[HWWriteResGroup75], (instregex "VZEROUPPER")>; -// VPMOVSX/ZX BW BD BQ DW DQ. -// y <- x. -def WriteVPMOVSX : SchedWriteRes<[HWPort5]> { - let Latency = 3; - let NumMicroOps = 1; +def HWWriteResGroup76 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> { + let Latency = 4; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; } -def : InstRW<[WriteVPMOVSX], (instregex "VPMOV(SX|ZX)(BW|BQ|DW|DQ)Yrr")>; - -// PBLENDW. -// x,x,i / v,v,v,i -def WritePBLENDWr : SchedWriteRes<[HWPort5]>; -def : InstRW<[WritePBLENDWr], (instregex "(V?)PBLENDW(Y?)rri")>; +def: InstRW<[HWWriteResGroup76], (instregex "LAR32rr")>; -// x,m,i / v,v,m,i -def WritePBLENDWm : SchedWriteRes<[HWPort5, HWPort23]> { - let NumMicroOps = 2; +def HWWriteResGroup77 : SchedWriteRes<[HWPort0,HWPort4,HWPort237,HWPort15]> { let Latency = 4; - let ResourceCycles = [1, 1]; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; } -def : InstRW<[WritePBLENDWm, ReadAfterLd], (instregex "(V?)PBLENDW(Y?)rmi")>; +def: InstRW<[HWWriteResGroup77], (instregex "VMASKMOVPDYrm")>; +def: InstRW<[HWWriteResGroup77], (instregex "VMASKMOVPDmr")>; +def: InstRW<[HWWriteResGroup77], (instregex "VMASKMOVPSmr")>; +def: InstRW<[HWWriteResGroup77], (instregex "VPMASKMOVDYmr")>; +def: InstRW<[HWWriteResGroup77], (instregex "VPMASKMOVDmr")>; +def: InstRW<[HWWriteResGroup77], (instregex "VPMASKMOVQYmr")>; +def: InstRW<[HWWriteResGroup77], (instregex "VPMASKMOVQmr")>; -// VPBLENDD. -// v,v,v,i. -def WriteVPBLENDDr : SchedWriteRes<[HWPort015]>; -def : InstRW<[WriteVPBLENDDr], (instregex "VPBLENDD(Y?)rri")>; - -// v,v,m,i -def WriteVPBLENDDm : SchedWriteRes<[HWPort015, HWPort23]> { - let NumMicroOps = 2; +def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort237]> { let Latency = 4; - let ResourceCycles = [1, 1]; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; } -def : InstRW<[WriteVPBLENDDm, ReadAfterLd], (instregex "VPBLENDD(Y?)rmi")>; +def: InstRW<[HWWriteResGroup78], (instregex "VCVTPS2PHmr")>; -// MASKMOVQ. -def WriteMASKMOVQ : SchedWriteRes<[HWPort0, HWPort4, HWPort23]> { - let Latency = 13; +def HWWriteResGroup79 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort0156]> { + let Latency = 4; let NumMicroOps = 4; - let ResourceCycles = [1, 1, 2]; + let ResourceCycles = [1,1,1,1]; } -def : InstRW<[WriteMASKMOVQ], (instregex "MMX_MASKMOVQ(64)?")>; +def: InstRW<[HWWriteResGroup79], (instregex "SHLD64mri8")>; +def: InstRW<[HWWriteResGroup79], (instregex "SHRD64mri8")>; -// MASKMOVDQU. -def WriteMASKMOVDQU : SchedWriteRes<[HWPort04, HWPort56, HWPort23]> { - let Latency = 14; - let NumMicroOps = 10; - let ResourceCycles = [4, 2, 4]; +def HWWriteResGroup80 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> { + let Latency = 4; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; } -def : InstRW<[WriteMASKMOVDQU], (instregex "(V?)MASKMOVDQU(64)?")>; +def: InstRW<[HWWriteResGroup80], (instregex "LAR32rm")>; +def: InstRW<[HWWriteResGroup80], (instregex "LSL32rm")>; -// VPMASKMOV D/Q. -// v,v,m. -def WriteVPMASKMOVr : SchedWriteRes<[HWPort5, HWPort23]> { +def HWWriteResGroup81 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { let Latency = 4; - let NumMicroOps = 3; - let ResourceCycles = [2, 1]; + let NumMicroOps = 6; + let ResourceCycles = [1,1,4]; } -def : InstRW<[WriteVPMASKMOVr, ReadAfterLd], - (instregex "VPMASKMOV(D|Q)(Y?)rm")>; +def: InstRW<[HWWriteResGroup81], (instregex "PUSHF16")>; +def: InstRW<[HWWriteResGroup81], (instregex "PUSHF64")>; -// m, v,v. -def WriteVPMASKMOVm : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> { - let Latency = 13; - let NumMicroOps = 4; - let ResourceCycles = [1, 1, 1, 1]; +def HWWriteResGroup82 : SchedWriteRes<[HWPort0]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; } -def : InstRW<[WriteVPMASKMOVm], (instregex "VPMASKMOV(D|Q)(Y?)mr")>; - -// PMOVMSKB. -def WritePMOVMSKB : SchedWriteRes<[HWPort0]> { - let Latency = 3; +def: InstRW<[HWWriteResGroup82], (instregex "MMX_PMADDUBSWrr64")>; +def: InstRW<[HWWriteResGroup82], (instregex "MMX_PMADDWDirr")>; +def: InstRW<[HWWriteResGroup82], (instregex "MMX_PMULHRSWrr64")>; +def: InstRW<[HWWriteResGroup82], (instregex "MMX_PMULHUWirr")>; +def: InstRW<[HWWriteResGroup82], (instregex "MMX_PMULHWirr")>; +def: InstRW<[HWWriteResGroup82], (instregex "MMX_PMULLWirr")>; +def: InstRW<[HWWriteResGroup82], (instregex "MMX_PMULUDQirr")>; +def: InstRW<[HWWriteResGroup82], (instregex "MMX_PSADBWirr")>; +def: InstRW<[HWWriteResGroup82], (instregex "PCMPGTQrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "PHMINPOSUWrr128")>; +def: InstRW<[HWWriteResGroup82], (instregex "PMADDUBSWrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "PMADDWDrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "PMULDQrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "PMULHRSWrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "PMULHUWrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "PMULHWrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "PMULLWrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "PMULUDQrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "PSADBWrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "RCPPSr")>; +def: InstRW<[HWWriteResGroup82], (instregex "RCPSSr")>; +def: InstRW<[HWWriteResGroup82], (instregex "RSQRTPSr")>; +def: InstRW<[HWWriteResGroup82], (instregex "RSQRTSSr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VMOVMSKPSYrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPCMPGTQYrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPCMPGTQrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPHMINPOSUWrr128")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMADDUBSWrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMADDUBSWrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMADDWDYrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMADDWDrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMULDQYrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMULDQrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMULHRSWYrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMULHRSWrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMULHUWrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMULHWYrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMULHWrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMULLWYrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMULLWrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPMULUDQrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPSADBWYrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VPSADBWrr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VRSQRTPSr")>; +def: InstRW<[HWWriteResGroup82], (instregex "VRSQRTSSr")>; + +def HWWriteResGroup83 : SchedWriteRes<[HWPort01]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; } -def : InstRW<[WritePMOVMSKB], (instregex "(V|MMX_)?PMOVMSKB(Y?)rr")>; - -// PEXTR B/W/D/Q. -// r32,x,i. -def WritePEXTRr : SchedWriteRes<[HWPort0, HWPort5]> { - let Latency = 2; +def: InstRW<[HWWriteResGroup83], (instregex "MULPDrr")>; +def: InstRW<[HWWriteResGroup83], (instregex "MULPSrr")>; +def: InstRW<[HWWriteResGroup83], (instregex "MULSDrr")>; +def: InstRW<[HWWriteResGroup83], (instregex "MULSSrr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD132PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD132PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD132PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD132PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD132SDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD132SSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD213PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD213PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD213PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD213PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD213SDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD213SSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD231PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD231PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD231PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD231PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD231SDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADD231SSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADDSUB132PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADDSUB132PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADDSUB132PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADDSUB132PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADDSUB213PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADDSUB213PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADDSUB213PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADDSUB213PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADDSUB231PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADDSUB231PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADDSUB231PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMADDSUB231PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB132PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB132PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB132PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB132PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB132SDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB132SSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB213PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB213PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB213PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB213PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB213SDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB213SSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB231PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB231PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB231PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB231PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB231SDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUB231SSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUBADD132PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUBADD132PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUBADD132PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUBADD132PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUBADD213PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUBADD213PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUBADD213PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUBADD213PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUBADD231PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUBADD231PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUBADD231PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFMSUBADD231PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD132PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD132PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD132PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD132PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD132SDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD132SSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD213PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD213PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD213PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD213PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD213SDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD213SSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD231PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD231PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD231PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD231PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD231SDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMADD231SSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB132PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB132PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB132PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB132PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB132SDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB132SSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB213PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB213PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB213PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB213PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB213SDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB213SSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB231PDYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB231PDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB231PSYr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB231PSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB231SDr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VFNMSUB231SSr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VMULPDYrr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VMULPDrr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VMULPSYrr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VMULPSrr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VMULSDrr")>; +def: InstRW<[HWWriteResGroup83], (instregex "VMULSSrr")>; + +def HWWriteResGroup84 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 5; let NumMicroOps = 2; - let ResourceCycles = [1, 1]; -} -def : InstRW<[WritePEXTRr], (instregex "PEXTR(B|W|D|Q)rr", "MMX_PEXTRWirri")>; - -// m8,x,i. -def WritePEXTRm : SchedWriteRes<[HWPort23, HWPort4, HWPort5]> { + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup84], (instregex "MMX_PMADDUBSWrm64")>; +def: InstRW<[HWWriteResGroup84], (instregex "MMX_PMADDWDirm")>; +def: InstRW<[HWWriteResGroup84], (instregex "MMX_PMULHRSWrm64")>; +def: InstRW<[HWWriteResGroup84], (instregex "MMX_PMULHUWirm")>; +def: InstRW<[HWWriteResGroup84], (instregex "MMX_PMULHWirm")>; +def: InstRW<[HWWriteResGroup84], (instregex "MMX_PMULLWirm")>; +def: InstRW<[HWWriteResGroup84], (instregex "MMX_PMULUDQirm")>; +def: InstRW<[HWWriteResGroup84], (instregex "MMX_PSADBWirm")>; +def: InstRW<[HWWriteResGroup84], (instregex "PCMPGTQrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "PHMINPOSUWrm128")>; +def: InstRW<[HWWriteResGroup84], (instregex "PMADDUBSWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "PMADDWDrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "PMULDQrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "PMULHRSWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "PMULHUWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "PMULHWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "PMULLWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "PMULUDQrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "PSADBWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "RCPPSm")>; +def: InstRW<[HWWriteResGroup84], (instregex "RCPSSm")>; +def: InstRW<[HWWriteResGroup84], (instregex "RSQRTPSm")>; +def: InstRW<[HWWriteResGroup84], (instregex "RSQRTSSm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPCMPGTQYrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPCMPGTQrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPHMINPOSUWrm128")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMADDUBSWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMADDUBSWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMADDWDYrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMADDWDrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMULDQYrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMULDQrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMULHRSWYrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMULHRSWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMULHUWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMULHUWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMULHWYrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMULHWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMULLWYrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMULLWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMULUDQrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPMULUDQrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPSADBWYrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VPSADBWrm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VRCPPSm(_Int)?")>; +def: InstRW<[HWWriteResGroup84], (instregex "VRCPSSm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VRSQRTPSm")>; +def: InstRW<[HWWriteResGroup84], (instregex "VRSQRTSSm")>; + +def HWWriteResGroup85 : SchedWriteRes<[HWPort01,HWPort23]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup85], (instregex "MULPDrm")>; +def: InstRW<[HWWriteResGroup85], (instregex "MULPSrm")>; +def: InstRW<[HWWriteResGroup85], (instregex "MULSDrm")>; +def: InstRW<[HWWriteResGroup85], (instregex "MULSSrm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD132PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD132PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD132PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD132PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD132SDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD132SSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD213PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD213PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD213PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD213PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD213SDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD213SSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD231PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD231PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD231PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD231PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD231SDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADD231SSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADDSUB132PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADDSUB132PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADDSUB132PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADDSUB132PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADDSUB213PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADDSUB213PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADDSUB213PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADDSUB213PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADDSUB231PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADDSUB231PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADDSUB231PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMADDSUB231PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB132PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB132PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB132PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB132PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB132SDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB132SSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB213PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB213PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB213PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB213PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB213SDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB213SSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB231PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB231PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB231PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB231PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB231SDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUB231SSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUBADD132PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUBADD132PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUBADD132PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUBADD132PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUBADD213PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUBADD213PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUBADD213PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUBADD213PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUBADD231PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUBADD231PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUBADD231PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFMSUBADD231PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD132PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD132PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD132PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD132PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD132SDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD132SSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD213PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD213PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD213PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD213PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD213SDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD213SSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD231PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD231PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD231PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD231PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD231SDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMADD231SSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB132PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB132PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB132PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB132PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB132SDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB132SSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB213PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB213PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB213PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB213PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB213SDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB213SSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB231PDYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB231PDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB231PSYm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB231PSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB231SDm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VFNMSUB231SSm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VMULPDYrm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VMULPDrm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VMULPSYrm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VMULPSrm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VMULSDrm")>; +def: InstRW<[HWWriteResGroup85], (instregex "VMULSSrm")>; + +def HWWriteResGroup86 : SchedWriteRes<[HWPort1,HWPort5]> { + let Latency = 5; let NumMicroOps = 3; - let ResourceCycles = [1, 1, 1]; -} -def : InstRW<[WritePEXTRm], (instregex "PEXTR(B|W|D|Q)mr")>; - -// VPBROADCAST B/W. -// x, m8/16. -def WriteVPBROADCAST128Ld : SchedWriteRes<[HWPort01, HWPort23, HWPort5]> { + let ResourceCycles = [1,2]; +} +def: InstRW<[HWWriteResGroup86], (instregex "CVTSI2SS64rr")>; +def: InstRW<[HWWriteResGroup86], (instregex "HADDPDrr")>; +def: InstRW<[HWWriteResGroup86], (instregex "HADDPSrr")>; +def: InstRW<[HWWriteResGroup86], (instregex "HSUBPDrr")>; +def: InstRW<[HWWriteResGroup86], (instregex "HSUBPSrr")>; +def: InstRW<[HWWriteResGroup86], (instregex "VCVTSI2SS64rr")>; +def: InstRW<[HWWriteResGroup86], (instregex "VHADDPDrr")>; +def: InstRW<[HWWriteResGroup86], (instregex "VHADDPSYrr")>; +def: InstRW<[HWWriteResGroup86], (instregex "VHADDPSrr")>; +def: InstRW<[HWWriteResGroup86], (instregex "VHSUBPDYrr")>; +def: InstRW<[HWWriteResGroup86], (instregex "VHSUBPDrr")>; +def: InstRW<[HWWriteResGroup86], (instregex "VHSUBPSYrr")>; +def: InstRW<[HWWriteResGroup86], (instregex "VHSUBPSrr")>; + +def HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort0]> { let Latency = 5; let NumMicroOps = 3; - let ResourceCycles = [1, 1, 1]; + let ResourceCycles = [1,1,1]; } -def : InstRW<[WriteVPBROADCAST128Ld, ReadAfterLd], - (instregex "VPBROADCAST(B|W)rm")>; +def: InstRW<[HWWriteResGroup87], (instregex "STR32r")>; -// y, m8/16 -def WriteVPBROADCAST256Ld : SchedWriteRes<[HWPort01, HWPort23, HWPort5]> { - let Latency = 7; +def HWWriteResGroup88 : SchedWriteRes<[HWPort1,HWPort0,HWPort0156]> { + let Latency = 5; let NumMicroOps = 3; - let ResourceCycles = [1, 1, 1]; -} -def : InstRW<[WriteVPBROADCAST256Ld, ReadAfterLd], - (instregex "VPBROADCAST(B|W)Yrm")>; - -// VPGATHERDD. -// x. -def WriteVPGATHERDD128 : SchedWriteRes<[]> { - let NumMicroOps = 20; + let ResourceCycles = [1,1,1]; } -def : InstRW<[WriteVPGATHERDD128, ReadAfterLd], (instregex "VPGATHERDDrm")>; +def: InstRW<[HWWriteResGroup88], (instregex "MULX32rr")>; -// y. -def WriteVPGATHERDD256 : SchedWriteRes<[]> { - let NumMicroOps = 34; -} -def : InstRW<[WriteVPGATHERDD256, ReadAfterLd], (instregex "VPGATHERDDYrm")>; - -// VPGATHERQD. -// x. -def WriteVPGATHERQD128 : SchedWriteRes<[]> { - let NumMicroOps = 15; -} -def : InstRW<[WriteVPGATHERQD128, ReadAfterLd], (instregex "VPGATHERQDrm")>; - -// y. -def WriteVPGATHERQD256 : SchedWriteRes<[]> { - let NumMicroOps = 22; -} -def : InstRW<[WriteVPGATHERQD256, ReadAfterLd], (instregex "VPGATHERQDYrm")>; - -// VPGATHERDQ. -// x. -def WriteVPGATHERDQ128 : SchedWriteRes<[]> { - let NumMicroOps = 12; +def HWWriteResGroup89 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[HWWriteResGroup89], (instregex "HADDPDrm")>; +def: InstRW<[HWWriteResGroup89], (instregex "HADDPSrm")>; +def: InstRW<[HWWriteResGroup89], (instregex "HSUBPDrm")>; +def: InstRW<[HWWriteResGroup89], (instregex "HSUBPSrm")>; +def: InstRW<[HWWriteResGroup89], (instregex "VHADDPDrm")>; +def: InstRW<[HWWriteResGroup89], (instregex "VHADDPDrm")>; +def: InstRW<[HWWriteResGroup89], (instregex "VHADDPSYrm")>; +def: InstRW<[HWWriteResGroup89], (instregex "VHADDPSrm")>; +def: InstRW<[HWWriteResGroup89], (instregex "VHSUBPDYrm")>; +def: InstRW<[HWWriteResGroup89], (instregex "VHSUBPDrm")>; +def: InstRW<[HWWriteResGroup89], (instregex "VHSUBPSYrm")>; +def: InstRW<[HWWriteResGroup89], (instregex "VHSUBPSrm")>; + +def HWWriteResGroup90 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; } -def : InstRW<[WriteVPGATHERDQ128, ReadAfterLd], (instregex "VPGATHERDQrm")>; +def: InstRW<[HWWriteResGroup90], (instregex "CVTTSS2SI64rm")>; -// y. -def WriteVPGATHERDQ256 : SchedWriteRes<[]> { - let NumMicroOps = 20; +def HWWriteResGroup91 : SchedWriteRes<[HWPort1,HWPort23,HWPort0,HWPort0156]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; } -def : InstRW<[WriteVPGATHERDQ256, ReadAfterLd], (instregex "VPGATHERDQYrm")>; +def: InstRW<[HWWriteResGroup91], (instregex "MULX32rm")>; -// VPGATHERQQ. -// x. -def WriteVPGATHERQQ128 : SchedWriteRes<[]> { - let NumMicroOps = 14; +def HWWriteResGroup92 : SchedWriteRes<[HWPort6,HWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; } -def : InstRW<[WriteVPGATHERQQ128, ReadAfterLd], (instregex "VPGATHERQQrm")>; +def: InstRW<[HWWriteResGroup92], (instregex "PAUSE")>; -// y. -def WriteVPGATHERQQ256 : SchedWriteRes<[]> { - let NumMicroOps = 22; +def HWWriteResGroup93 : SchedWriteRes<[HWPort0,HWPort0156]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,4]; } -def : InstRW<[WriteVPGATHERQQ256, ReadAfterLd], (instregex "VPGATHERQQYrm")>; +def: InstRW<[HWWriteResGroup93], (instregex "XSETBV")>; -//-- Arithmetic instructions --// - -//////////////////////////////////////////////////////////////////////////////// -// Horizontal add/sub instructions. -//////////////////////////////////////////////////////////////////////////////// - -// HADD, HSUB PS/PD -// x,x / v,v,v. -def : WriteRes<WriteFHAdd, [HWPort1, HWPort5]> { +def HWWriteResGroup94 : SchedWriteRes<[HWPort0,HWPort0156]> { let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [2,3]; +} +def: InstRW<[HWWriteResGroup94], (instregex "CMPXCHG32rr")>; +def: InstRW<[HWWriteResGroup94], (instregex "CMPXCHG8rr")>; +def: InstRW<[HWWriteResGroup94], (instregex "ROUNDPDr")>; +def: InstRW<[HWWriteResGroup94], (instregex "ROUNDPSr")>; +def: InstRW<[HWWriteResGroup94], (instregex "ROUNDSDr")>; +def: InstRW<[HWWriteResGroup94], (instregex "ROUNDSSr")>; +def: InstRW<[HWWriteResGroup94], (instregex "VBROADCASTF128")>; +def: InstRW<[HWWriteResGroup94], (instregex "VPBROADCASTMB2QZrr")>; +def: InstRW<[HWWriteResGroup94], (instregex "VROUNDPDr")>; +def: InstRW<[HWWriteResGroup94], (instregex "VROUNDPSr")>; +def: InstRW<[HWWriteResGroup94], (instregex "VROUNDSDr")>; + +def HWWriteResGroup95 : SchedWriteRes<[HWPort1,HWPort5]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup95], (instregex "VCVTDQ2PDYrr")>; +def: InstRW<[HWWriteResGroup95], (instregex "VCVTPD2DQYrr")>; +def: InstRW<[HWWriteResGroup95], (instregex "VCVTPD2PSYrr")>; +def: InstRW<[HWWriteResGroup95], (instregex "VCVTPS2PHYrr")>; +def: InstRW<[HWWriteResGroup95], (instregex "VCVTTPD2DQYrr")>; +def: InstRW<[HWWriteResGroup95], (instregex "ROUNDPDm")>; +def: InstRW<[HWWriteResGroup95], (instregex "ROUNDPSm")>; +def: InstRW<[HWWriteResGroup95], (instregex "ROUNDSDm")>; +def: InstRW<[HWWriteResGroup95], (instregex "ROUNDSSm")>; +def: InstRW<[HWWriteResGroup95], (instregex "VROUNDPDm")>; +def: InstRW<[HWWriteResGroup95], (instregex "VROUNDPDm")>; +def: InstRW<[HWWriteResGroup95], (instregex "VROUNDPSm")>; +def: InstRW<[HWWriteResGroup95], (instregex "VROUNDPSm")>; +def: InstRW<[HWWriteResGroup95], (instregex "VROUNDSDm")>; +def: InstRW<[HWWriteResGroup95], (instregex "VROUNDSSm")>; + +def HWWriteResGroup96 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { + let Latency = 6; let NumMicroOps = 3; - let ResourceCycles = [1, 2]; + let ResourceCycles = [1,1,1]; } +def: InstRW<[HWWriteResGroup96], (instregex "VCVTDQ2PDYrm")>; -// x,m / v,v,m. -def : WriteRes<WriteFHAddLd, [HWPort1, HWPort5, HWPort23]> { - let Latency = 9; +def HWWriteResGroup97 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort237]> { + let Latency = 6; let NumMicroOps = 4; - let ResourceCycles = [1, 2, 1]; + let ResourceCycles = [1,1,1,1]; } +def: InstRW<[HWWriteResGroup97], (instregex "VCVTPS2PHYmr")>; -// PHADD|PHSUB (S) W/D. -// v <- v,v. -def : WriteRes<WritePHAdd, [HWPort1, HWPort5]> { - let Latency = 3; - let NumMicroOps = 3; - let ResourceCycles = [1, 2]; -} -// v <- v,m. -def : WriteRes<WritePHAddLd, [HWPort1, HWPort5, HWPort23]> { +def HWWriteResGroup98 : SchedWriteRes<[HWPort1,HWPort6,HWPort0,HWPort0156]> { let Latency = 6; - let NumMicroOps = 3; - let ResourceCycles = [1, 2, 1]; -} - -// PHADD|PHSUB (S) W/D. -// v <- v,v. -def WritePHADDSUBr : SchedWriteRes<[HWPort1, HWPort5]> { - let Latency = 3; - let NumMicroOps = 3; - let ResourceCycles = [1, 2]; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; } -def : InstRW<[WritePHADDSUBr], (instregex "MMX_PHADD(W?)rr64", - "MMX_PHADDSWrr64", - "MMX_PHSUB(W|D)rr64", - "MMX_PHSUBSWrr64", - "(V?)PH(ADD|SUB)(W|D)(Y?)rr", - "(V?)PH(ADD|SUB)SWrr(256)?")>; +def: InstRW<[HWWriteResGroup98], (instregex "SLDT32r")>; -// v <- v,m. -def WritePHADDSUBm : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> { +def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> { let Latency = 6; - let NumMicroOps = 3; - let ResourceCycles = [1, 2, 1]; + let NumMicroOps = 6; + let ResourceCycles = [1,5]; } -def : InstRW<[WritePHADDSUBm, ReadAfterLd], - (instregex "MMX_PHADD(W?)rm64", - "MMX_PHADDSWrm64", - "MMX_PHSUB(W|D)rm64", - "MMX_PHSUBSWrm64", - "(V?)PH(ADD|SUB)(W|D)(Y?)rm", - "(V?)PH(ADD|SUB)SWrm(128|256)?")>; +def: InstRW<[HWWriteResGroup99], (instregex "STD")>; -// PCMPGTQ. -// v <- v,v. -def WritePCMPGTQr : SchedWriteRes<[HWPort0]> { - let Latency = 5; +def HWWriteResGroup100 : SchedWriteRes<[HWPort5]> { + let Latency = 7; let NumMicroOps = 1; + let ResourceCycles = [1]; } -def : InstRW<[WritePCMPGTQr], (instregex "(V?)PCMPGTQ(Y?)rr")>; - -// v <- v,m. -def WritePCMPGTQm : SchedWriteRes<[HWPort0, HWPort23]> { - let Latency = 5; - let NumMicroOps = 2; - let ResourceCycles = [1, 1]; -} -def : InstRW<[WritePCMPGTQm, ReadAfterLd], (instregex "(V?)PCMPGTQ(Y?)rm")>; +def: InstRW<[HWWriteResGroup100], (instregex "AESDECLASTrr")>; +def: InstRW<[HWWriteResGroup100], (instregex "AESDECrr")>; +def: InstRW<[HWWriteResGroup100], (instregex "AESENCLASTrr")>; +def: InstRW<[HWWriteResGroup100], (instregex "AESENCrr")>; +def: InstRW<[HWWriteResGroup100], (instregex "KANDQrr")>; +def: InstRW<[HWWriteResGroup100], (instregex "VAESDECLASTrr")>; +def: InstRW<[HWWriteResGroup100], (instregex "VAESDECrr")>; +def: InstRW<[HWWriteResGroup100], (instregex "VAESENCrr")>; -// PMULLD. -// x,x / y,y,y. -def WritePMULLDr : SchedWriteRes<[HWPort0]> { - let Latency = 10; +def HWWriteResGroup101 : SchedWriteRes<[HWPort5,HWPort23]> { + let Latency = 7; let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def : InstRW<[WritePMULLDr], (instregex "(V?)PMULLD(Y?)rr")>; - -// x,m / y,y,m. -def WritePMULLDm : SchedWriteRes<[HWPort0, HWPort23]> { - let Latency = 10; + let ResourceCycles = [1,1]; +} +def: InstRW<[HWWriteResGroup101], (instregex "AESDECLASTrm")>; +def: InstRW<[HWWriteResGroup101], (instregex "AESDECrm")>; +def: InstRW<[HWWriteResGroup101], (instregex "AESENCLASTrm")>; +def: InstRW<[HWWriteResGroup101], (instregex "AESENCrm")>; +def: InstRW<[HWWriteResGroup101], (instregex "VAESDECLASTrm")>; +def: InstRW<[HWWriteResGroup101], (instregex "VAESDECrm")>; +def: InstRW<[HWWriteResGroup101], (instregex "VAESENCLASTrm")>; +def: InstRW<[HWWriteResGroup101], (instregex "VAESENCrm")>; + +def HWWriteResGroup102 : SchedWriteRes<[HWPort0,HWPort5]> { + let Latency = 7; let NumMicroOps = 3; - let ResourceCycles = [2, 1]; + let ResourceCycles = [1,2]; } -def : InstRW<[WritePMULLDm, ReadAfterLd], (instregex "(V?)PMULLD(Y?)rm")>; - -//-- Logic instructions --// +def: InstRW<[HWWriteResGroup102], (instregex "MPSADBWrri")>; +def: InstRW<[HWWriteResGroup102], (instregex "VMPSADBWYrri")>; +def: InstRW<[HWWriteResGroup102], (instregex "VMPSADBWrri")>; -// PTEST. -// v,v. -def WritePTESTr : SchedWriteRes<[HWPort0, HWPort5]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [1, 1]; +def HWWriteResGroup103 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; } -def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rr")>; +def: InstRW<[HWWriteResGroup103], (instregex "MPSADBWrmi")>; +def: InstRW<[HWWriteResGroup103], (instregex "VMPSADBWYrmi")>; +def: InstRW<[HWWriteResGroup103], (instregex "VMPSADBWrmi")>; -// v,m. -def WritePTESTm : SchedWriteRes<[HWPort0, HWPort5, HWPort23]> { - let Latency = 6; +def HWWriteResGroup104 : SchedWriteRes<[HWPort0,HWPort1,HWPort5]> { + let Latency = 9; let NumMicroOps = 3; - let ResourceCycles = [1, 1, 1]; + let ResourceCycles = [1,1,1]; } -def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rm")>; +def: InstRW<[HWWriteResGroup104], (instregex "DPPDrri")>; +def: InstRW<[HWWriteResGroup104], (instregex "VDPPDrri")>; -// PSLL,PSRL,PSRA W/D/Q. -// x,x / v,v,x. -def WritePShift : SchedWriteRes<[HWPort0, HWPort5]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [1, 1]; +def HWWriteResGroup105 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; } -def : InstRW<[WritePShift], (instregex "(V?)PS(LL|RL|RA)(W|D|Q)(Y?)rr")>; +def: InstRW<[HWWriteResGroup105], (instregex "DPPDrmi")>; +def: InstRW<[HWWriteResGroup105], (instregex "VDPPDrmi")>; -// PSLL,PSRL DQ. -def : InstRW<[WriteP5], (instregex "(V?)PS(R|L)LDQ(Y?)ri")>; - -//-- Other --// - -// EMMS. -def WriteEMMS : SchedWriteRes<[]> { - let Latency = 13; - let NumMicroOps = 31; +def HWWriteResGroup106 : SchedWriteRes<[HWPort0]> { + let Latency = 10; + let NumMicroOps = 2; + let ResourceCycles = [2]; } -def : InstRW<[WriteEMMS], (instregex "MMX_EMMS")>; - -//=== Floating Point XMM and YMM Instructions ===// -//-- Move instructions --// +def: InstRW<[HWWriteResGroup106], (instregex "PMULLDrr")>; +def: InstRW<[HWWriteResGroup106], (instregex "VPMULLDYrr")>; +def: InstRW<[HWWriteResGroup106], (instregex "VPMULLDrr")>; -// MOVMSKP S/D. -// r32 <- x. -def WriteMOVMSKPr : SchedWriteRes<[HWPort0]> { - let Latency = 3; +def HWWriteResGroup107 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; } -def : InstRW<[WriteMOVMSKPr], (instregex "(V?)MOVMSKP(S|D)rr")>; +def: InstRW<[HWWriteResGroup107], (instregex "PMULLDrm")>; +def: InstRW<[HWWriteResGroup107], (instregex "VPMULLDYrm")>; +def: InstRW<[HWWriteResGroup107], (instregex "VPMULLDrm")>; -// r32 <- y. -def WriteVMOVMSKPYr : SchedWriteRes<[HWPort0]> { - let Latency = 2; +def HWWriteResGroup108 : SchedWriteRes<[HWPort0]> { + let Latency = 11; + let NumMicroOps = 1; + let ResourceCycles = [1]; } -def : InstRW<[WriteVMOVMSKPYr], (instregex "VMOVMSKP(S|D)Yrr")>; - -// VPERM2F128. -def : InstRW<[WriteFShuffle256], (instregex "VPERM2F128rr")>; -def : InstRW<[WriteFShuffle256Ld, ReadAfterLd], (instregex "VPERM2F128rm")>; +def: InstRW<[HWWriteResGroup108], (instregex "DIVPSrr")>; +def: InstRW<[HWWriteResGroup108], (instregex "DIVSSrr")>; -// BLENDVP S/D. -def : InstRW<[WriteFVarBlend], (instregex "BLENDVP(S|D)rr0")>; -def : InstRW<[WriteFVarBlendLd, ReadAfterLd], (instregex "BLENDVP(S|D)rm0")>; - -// VBROADCASTF128. -def : InstRW<[WriteLoad], (instregex "VBROADCASTF128")>; - -// EXTRACTPS. -// r32,x,i. -def WriteEXTRACTPSr : SchedWriteRes<[HWPort0, HWPort5]> { +def HWWriteResGroup109 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 11; let NumMicroOps = 2; - let ResourceCycles = [1, 1]; + let ResourceCycles = [1,1]; } -def : InstRW<[WriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>; +def: InstRW<[HWWriteResGroup109], (instregex "DIVPSrm")>; +def: InstRW<[HWWriteResGroup109], (instregex "DIVSSrm")>; -// m32,x,i. -def WriteEXTRACTPSm : SchedWriteRes<[HWPort0, HWPort5, HWPort23]> { - let Latency = 4; +def HWWriteResGroup110 : SchedWriteRes<[HWPort0]> { + let Latency = 11; let NumMicroOps = 3; - let ResourceCycles = [1, 1, 1]; -} -def : InstRW<[WriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>; - -// VEXTRACTF128. -// x,y,i. -def : InstRW<[WriteFShuffle256], (instregex "VEXTRACTF128rr")>; - -// m128,y,i. -def WriteVEXTRACTF128m : SchedWriteRes<[HWPort23, HWPort4]> { - let Latency = 4; - let NumMicroOps = 2; - let ResourceCycles = [1, 1]; + let ResourceCycles = [3]; } -def : InstRW<[WriteVEXTRACTF128m], (instregex "VEXTRACTF128mr")>; +def: InstRW<[HWWriteResGroup110], (instregex "PCMPISTRIrr")>; +def: InstRW<[HWWriteResGroup110], (instregex "PCMPISTRM128rr")>; +def: InstRW<[HWWriteResGroup110], (instregex "VPCMPISTRIrr")>; +def: InstRW<[HWWriteResGroup110], (instregex "VPCMPISTRM128rr")>; -// VINSERTF128. -// y,y,x,i. -def : InstRW<[WriteFShuffle256], (instregex "VINSERTF128rr")>; - -// y,y,m128,i. -def WriteVINSERTF128m : SchedWriteRes<[HWPort015, HWPort23]> { - let Latency = 4; - let NumMicroOps = 2; - let ResourceCycles = [1, 1]; +def HWWriteResGroup111 : SchedWriteRes<[HWPort0,HWPort5]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; } -def : InstRW<[WriteFShuffle256, ReadAfterLd], (instregex "VINSERTF128rm")>; +def: InstRW<[HWWriteResGroup111], (instregex "PCLMULQDQrr")>; +def: InstRW<[HWWriteResGroup111], (instregex "VPCLMULQDQrr")>; -// VMASKMOVP S/D. -// v,v,m. -def WriteVMASKMOVPrm : SchedWriteRes<[HWPort5, HWPort23]> { - let Latency = 4; +def HWWriteResGroup112 : SchedWriteRes<[HWPort0,HWPort015]> { + let Latency = 11; let NumMicroOps = 3; - let ResourceCycles = [2, 1]; + let ResourceCycles = [2,1]; } -def : InstRW<[WriteVMASKMOVPrm], (instregex "VMASKMOVP(S|D)(Y?)rm")>; +def: InstRW<[HWWriteResGroup112], (instregex "VRCPPSYr(_Int)?")>; +def: InstRW<[HWWriteResGroup112], (instregex "VRSQRTPSYr")>; -// m128,x,x. -def WriteVMASKMOVPmr : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> { - let Latency = 13; +def HWWriteResGroup113 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 11; let NumMicroOps = 4; - let ResourceCycles = [1, 1, 1, 1]; + let ResourceCycles = [3,1]; } -def : InstRW<[WriteVMASKMOVPmr], (instregex "VMASKMOVP(S|D)mr")>; +def: InstRW<[HWWriteResGroup113], (instregex "PCMPISTRIrm")>; +def: InstRW<[HWWriteResGroup113], (instregex "PCMPISTRM128rm")>; +def: InstRW<[HWWriteResGroup113], (instregex "VPCMPISTRIrm")>; +def: InstRW<[HWWriteResGroup113], (instregex "VPCMPISTRM128rm")>; -// m256,y,y. -def WriteVMASKMOVPYmr : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> { - let Latency = 14; +def HWWriteResGroup114 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> { + let Latency = 11; let NumMicroOps = 4; - let ResourceCycles = [1, 1, 1, 1]; + let ResourceCycles = [2,1,1]; } -def : InstRW<[WriteVMASKMOVPYmr], (instregex "VMASKMOVP(S|D)Ymr")>; +def: InstRW<[HWWriteResGroup114], (instregex "PCLMULQDQrm")>; +def: InstRW<[HWWriteResGroup114], (instregex "VPCLMULQDQrm")>; +def: InstRW<[HWWriteResGroup114], (instregex "VRCPPSYm(_Int)?")>; -// VGATHERDPS. -// x. -def WriteVGATHERDPS128 : SchedWriteRes<[]> { - let NumMicroOps = 20; -} -def : InstRW<[WriteVGATHERDPS128, ReadAfterLd], (instregex "VGATHERDPSrm")>; - -// y. -def WriteVGATHERDPS256 : SchedWriteRes<[]> { - let NumMicroOps = 34; -} -def : InstRW<[WriteVGATHERDPS256, ReadAfterLd], (instregex "VGATHERDPSYrm")>; - -// VGATHERQPS. -// x. -def WriteVGATHERQPS128 : SchedWriteRes<[]> { - let NumMicroOps = 15; -} -def : InstRW<[WriteVGATHERQPS128, ReadAfterLd], (instregex "VGATHERQPSrm")>; - -// y. -def WriteVGATHERQPS256 : SchedWriteRes<[]> { - let NumMicroOps = 22; -} -def : InstRW<[WriteVGATHERQPS256, ReadAfterLd], (instregex "VGATHERQPSYrm")>; - -// VGATHERDPD. -// x. -def WriteVGATHERDPD128 : SchedWriteRes<[]> { - let NumMicroOps = 12; -} -def : InstRW<[WriteVGATHERDPD128, ReadAfterLd], (instregex "VGATHERDPDrm")>; - -// y. -def WriteVGATHERDPD256 : SchedWriteRes<[]> { - let NumMicroOps = 20; +def HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort23,HWPort015]> { + let Latency = 11; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; } -def : InstRW<[WriteVGATHERDPD256, ReadAfterLd], (instregex "VGATHERDPDYrm")>; +def: InstRW<[HWWriteResGroup115], (instregex "VRCPPSm")>; +def: InstRW<[HWWriteResGroup115], (instregex "VRSQRTPSYm")>; -// VGATHERQPD. -// x. -def WriteVGATHERQPD128 : SchedWriteRes<[]> { +def HWWriteResGroup116 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0,HWPort15,HWPort0156]> { + let Latency = 11; let NumMicroOps = 14; + let ResourceCycles = [1,1,1,4,2,5]; } -def : InstRW<[WriteVGATHERQPD128, ReadAfterLd], (instregex "VGATHERQPDrm")>; +def: InstRW<[HWWriteResGroup116], (instregex "CMPXCHG8B")>; -// y. -def WriteVGATHERQPD256 : SchedWriteRes<[]> { - let NumMicroOps = 22; +def HWWriteResGroup117 : SchedWriteRes<[HWPort0]> { + let Latency = 13; + let NumMicroOps = 1; + let ResourceCycles = [1]; } -def : InstRW<[WriteVGATHERQPD256, ReadAfterLd], (instregex "VGATHERQPDYrm")>; - -//-- Conversion instructions --// - -// CVTPD2PS. -// x,x. -def : InstRW<[WriteP1_P5_Lat4], (instregex "(V?)CVTPD2PSrr")>; - -// x,m128. -def : InstRW<[WriteP1_P5_Lat4Ld], (instregex "(V?)CVTPD2PS(X?)rm")>; +def: InstRW<[HWWriteResGroup117], (instregex "SQRTPSr")>; +def: InstRW<[HWWriteResGroup117], (instregex "SQRTSSr")>; +def: InstRW<[HWWriteResGroup117], (instregex "VDIVPSrr")>; +def: InstRW<[HWWriteResGroup117], (instregex "VDIVSSrr")>; -// x,y. -def WriteCVTPD2PSYrr : SchedWriteRes<[HWPort1, HWPort5]> { - let Latency = 5; +def HWWriteResGroup118 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 13; let NumMicroOps = 2; - let ResourceCycles = [1, 1]; + let ResourceCycles = [1,1]; } -def : InstRW<[WriteCVTPD2PSYrr], (instregex "(V?)CVTPD2PSYrr")>; +def: InstRW<[HWWriteResGroup118], (instregex "SQRTPSm")>; +def: InstRW<[HWWriteResGroup118], (instregex "SQRTSSm")>; +def: InstRW<[HWWriteResGroup118], (instregex "VDIVPSrm")>; +def: InstRW<[HWWriteResGroup118], (instregex "VDIVSSrm")>; -// x,m256. -def WriteCVTPD2PSYrm : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> { - let Latency = 9; - let NumMicroOps = 3; - let ResourceCycles = [1, 1, 1]; +def HWWriteResGroup119 : SchedWriteRes<[HWPort0]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1]; } -def : InstRW<[WriteCVTPD2PSYrm], (instregex "(V?)CVTPD2PSYrm")>; - -// CVTSD2SS. -// x,x. -def : InstRW<[WriteP1_P5_Lat4], (instregex "(Int_)?(V)?CVTSD2SSrr")>; - -// x,m64. -def : InstRW<[WriteP1_P5_Lat4Ld], (instregex "(Int_)?(V)?CVTSD2SSrm")>; +def: InstRW<[HWWriteResGroup119], (instregex "DIVPDrr")>; +def: InstRW<[HWWriteResGroup119], (instregex "DIVSDrr")>; +def: InstRW<[HWWriteResGroup119], (instregex "VSQRTPSr")>; +def: InstRW<[HWWriteResGroup119], (instregex "VSQRTSSr")>; -// CVTPS2PD. -// x,x. -def WriteCVTPS2PDrr : SchedWriteRes<[HWPort0, HWPort5]> { - let Latency = 2; +def HWWriteResGroup120 : SchedWriteRes<[HWPort5]> { + let Latency = 14; let NumMicroOps = 2; - let ResourceCycles = [1, 1]; + let ResourceCycles = [2]; } -def : InstRW<[WriteCVTPS2PDrr], (instregex "(V?)CVTPS2PDrr")>; +def: InstRW<[HWWriteResGroup120], (instregex "AESIMCrr")>; +def: InstRW<[HWWriteResGroup120], (instregex "VAESIMCrr")>; -// x,m64. -// y,m128. -def WriteCVTPS2PDrm : SchedWriteRes<[HWPort0, HWPort23]> { - let Latency = 5; +def HWWriteResGroup121 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 14; let NumMicroOps = 2; - let ResourceCycles = [1, 1]; + let ResourceCycles = [1,1]; } -def : InstRW<[WriteCVTPS2PDrm], (instregex "(V?)CVTPS2PD(Y?)rm")>; +def: InstRW<[HWWriteResGroup121], (instregex "DIVPDrm")>; +def: InstRW<[HWWriteResGroup121], (instregex "DIVSDrm")>; +def: InstRW<[HWWriteResGroup121], (instregex "VSQRTPSm")>; +def: InstRW<[HWWriteResGroup121], (instregex "VSQRTSSm")>; -// y,x. -def WriteVCVTPS2PDYrr : SchedWriteRes<[HWPort0, HWPort5]> { - let Latency = 5; - let NumMicroOps = 2; - let ResourceCycles = [1, 1]; +def HWWriteResGroup122 : SchedWriteRes<[HWPort5,HWPort23]> { + let Latency = 14; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; } -def : InstRW<[WriteVCVTPS2PDYrr], (instregex "VCVTPS2PDYrr")>; +def: InstRW<[HWWriteResGroup122], (instregex "AESIMCrm")>; +def: InstRW<[HWWriteResGroup122], (instregex "VAESIMCrm")>; -// CVTSS2SD. -// x,x. -def WriteCVTSS2SDrr : SchedWriteRes<[HWPort0, HWPort5]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [1, 1]; +def HWWriteResGroup123 : SchedWriteRes<[HWPort0,HWPort1,HWPort5]> { + let Latency = 14; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; } -def : InstRW<[WriteCVTSS2SDrr], (instregex "(Int_)?(V?)CVTSS2SDrr")>; +def: InstRW<[HWWriteResGroup123], (instregex "DPPSrri")>; +def: InstRW<[HWWriteResGroup123], (instregex "VDPPSYrri")>; +def: InstRW<[HWWriteResGroup123], (instregex "VDPPSrri")>; -// x,m32. -def WriteCVTSS2SDrm : SchedWriteRes<[HWPort0, HWPort23]> { - let Latency = 5; - let NumMicroOps = 2; - let ResourceCycles = [1, 1]; +def HWWriteResGroup124 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> { + let Latency = 14; + let NumMicroOps = 5; + let ResourceCycles = [2,1,1,1]; } -def : InstRW<[WriteCVTSS2SDrm], (instregex "(Int_)?(V?)CVTSS2SDrm")>; - -// CVTDQ2PD. -// x,x. -def : InstRW<[WriteP1_P5_Lat4], (instregex "(V)?CVTDQ2PDrr")>; - -// y,x. -def : InstRW<[WriteP1_P5_Lat6], (instregex "VCVTDQ2PDYrr")>; - -// CVT(T)PD2DQ. -// x,x. -def : InstRW<[WriteP1_P5_Lat4], (instregex "(V?)CVT(T?)PD2DQrr")>; -// x,m128. -def : InstRW<[WriteP1_P5_Lat4Ld], (instregex "(V?)CVT(T?)PD2DQrm")>; -// x,y. -def : InstRW<[WriteP1_P5_Lat6], (instregex "VCVT(T?)PD2DQYrr")>; -// x,m256. -def : InstRW<[WriteP1_P5_Lat6Ld], (instregex "VCVT(T?)PD2DQYrm")>; - -// CVT(T)PS2PI. -// mm,x. -def : InstRW<[WriteP1_P5_Lat4], (instregex "MMX_CVT(T?)PS2PIirr")>; - -// CVTPI2PD. -// x,mm. -def : InstRW<[WriteP1_P5_Lat4], (instregex "MMX_CVT(T?)PI2PDirr")>; - -// CVT(T)PD2PI. -// mm,x. -def : InstRW<[WriteP1_P5_Lat4], (instregex "MMX_CVT(T?)PD2PIirr")>; - -// CVSTSI2SS. -// x,r32. -def : InstRW<[WriteP1_P5_Lat4], (instregex "(Int_)?(V?)CVT(T?)SI2SS(64)?rr")>; - -// CVT(T)SS2SI. -// r32,x. -def : InstRW<[WriteP0_P1_Lat4], (instregex "(Int_)?(V?)CVT(T?)SS2SI(64)?rr")>; -// r32,m32. -def : InstRW<[WriteP0_P1_Lat4Ld], (instregex "(Int_)?(V?)CVT(T?)SS2SI(64)?rm")>; - -// CVTSI2SD. -// x,r32/64. -def : InstRW<[WriteP0_P1_Lat4], (instregex "(Int_)?(V?)CVTSI2SS(64)?rr")>; - -// CVTSD2SI. -// r32/64 -def : InstRW<[WriteP0_P1_Lat4], (instregex "(Int_)?(V?)CVT(T?)SD2SI(64)?rr")>; -// r32,m32. -def : InstRW<[WriteP0_P1_Lat4Ld], (instregex "(Int_)?(V?)CVT(T?)SD2SI(64)?rm")>; - -// VCVTPS2PH. -// x,v,i. -def : InstRW<[WriteP1_P5_Lat4], (instregex "VCVTPS2PH(Y?)rr")>; -// m,v,i. -def : InstRW<[WriteP1_P5_Lat4Ld, WriteRMW], (instregex "VCVTPS2PH(Y?)mr")>; - -// VCVTPH2PS. -// v,x. -def : InstRW<[WriteP1_P5_Lat4], (instregex "VCVTPH2PS(Y?)rr")>; - -//-- Arithmetic instructions --// +def: InstRW<[HWWriteResGroup124], (instregex "DPPSrmi")>; +def: InstRW<[HWWriteResGroup124], (instregex "VDPPSYrmi")>; +def: InstRW<[HWWriteResGroup124], (instregex "VDPPSrmi")>; -// HADD, HSUB PS/PD -// x,x / v,v,v. -def WriteHADDSUBPr : SchedWriteRes<[HWPort1, HWPort5]> { - let Latency = 5; - let NumMicroOps = 3; - let ResourceCycles = [1, 2]; +def HWWriteResGroup125 : SchedWriteRes<[HWPort23,HWPort0156]> { + let Latency = 14; + let NumMicroOps = 15; + let ResourceCycles = [1,14]; } -def : InstRW<[WriteHADDSUBPr], (instregex "(V?)H(ADD|SUB)P(S|D)(Y?)rr")>; +def: InstRW<[HWWriteResGroup125], (instregex "POPF16")>; -// x,m / v,v,m. -def WriteHADDSUBPm : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> { - let Latency = 9; - let NumMicroOps = 4; - let ResourceCycles = [1, 2, 1]; +def HWWriteResGroup126 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort0,HWPort0156]> { + let Latency = 15; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,1,1,1,2]; } -def : InstRW<[WriteHADDSUBPm], (instregex "(V?)H(ADD|SUB)P(S|D)(Y?)rm")>; +def: InstRW<[HWWriteResGroup126], (instregex "INSB")>; +def: InstRW<[HWWriteResGroup126], (instregex "INSL")>; +def: InstRW<[HWWriteResGroup126], (instregex "INSW")>; -// MULL SS/SD PS/PD. -// x,x / v,v,v. -def WriteMULr : SchedWriteRes<[HWPort01]> { - let Latency = 5; +def HWWriteResGroup127 : SchedWriteRes<[HWPort5]> { + let Latency = 16; + let NumMicroOps = 16; + let ResourceCycles = [16]; } -def : InstRW<[WriteMULr], (instregex "(V?)MUL(P|S)(S|D)rr")>; +def: InstRW<[HWWriteResGroup127], (instregex "VZEROALL")>; -// x,m / v,v,m. -def WriteMULm : SchedWriteRes<[HWPort01, HWPort23]> { - let Latency = 9; - let NumMicroOps = 2; - let ResourceCycles = [1, 1]; +def HWWriteResGroup128 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort0,HWPort0156]> { + let Latency = 16; + let NumMicroOps = 19; + let ResourceCycles = [2,1,4,1,1,4,6]; } -def : InstRW<[WriteMULm], (instregex "(V?)MUL(P|S)(S|D)rm")>; +def: InstRW<[HWWriteResGroup128], (instregex "CMPXCHG16B")>; -// VDIVPS. -// y,y,y. -def WriteVDIVPSYrr : SchedWriteRes<[HWPort0, HWPort15]> { - let Latency = 19; // 18-21 cycles. - let NumMicroOps = 3; - let ResourceCycles = [2, 1]; +def HWWriteResGroup129 : SchedWriteRes<[HWPort0,HWPort5,HWPort0156]> { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [4,3,1]; } -def : InstRW<[WriteVDIVPSYrr], (instregex "VDIVPSYrr")>; +def: InstRW<[HWWriteResGroup129], (instregex "PCMPESTRIrr")>; +def: InstRW<[HWWriteResGroup129], (instregex "VPCMPESTRIrr")>; -// y,y,m256. -def WriteVDIVPSYrm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> { - let Latency = 23; // 18-21 + 4 cycles. - let NumMicroOps = 4; - let ResourceCycles = [2, 1, 1]; +def HWWriteResGroup130 : SchedWriteRes<[HWPort5,HWPort6,HWPort0,HWPort0156]> { + let Latency = 18; + let NumMicroOps = 8; + let ResourceCycles = [1,1,1,5]; } -def : InstRW<[WriteVDIVPSYrm, ReadAfterLd], (instregex "VDIVPSYrm")>; +def: InstRW<[HWWriteResGroup130], (instregex "CPUID")>; +def: InstRW<[HWWriteResGroup130], (instregex "RDTSC")>; -// VDIVPD. -// y,y,y. -def WriteVDIVPDYrr : SchedWriteRes<[HWPort0, HWPort15]> { - let Latency = 27; // 19-35 cycles. - let NumMicroOps = 3; - let ResourceCycles = [2, 1]; +def HWWriteResGroup131 : SchedWriteRes<[HWPort0,HWPort5,HWPort23,HWPort0156]> { + let Latency = 18; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; } -def : InstRW<[WriteVDIVPDYrr], (instregex "VDIVPDYrr")>; +def: InstRW<[HWWriteResGroup131], (instregex "PCMPESTRIrm")>; +def: InstRW<[HWWriteResGroup131], (instregex "VPCMPESTRIrm")>; -// y,y,m256. -def WriteVDIVPDYrm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> { - let Latency = 31; // 19-35 + 4 cycles. - let NumMicroOps = 4; - let ResourceCycles = [2, 1, 1]; +def HWWriteResGroup132 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { + let Latency = 18; + let NumMicroOps = 19; + let ResourceCycles = [3,1,15]; } -def : InstRW<[WriteVDIVPDYrm, ReadAfterLd], (instregex "VDIVPDYrm")>; +def: InstRW<[HWWriteResGroup132], (instregex "XRSTOR")>; -// VRCPPS. -// y,y. -def WriteVRCPPSr : SchedWriteRes<[HWPort0, HWPort15]> { - let Latency = 7; - let NumMicroOps = 3; - let ResourceCycles = [2, 1]; +def HWWriteResGroup133 : SchedWriteRes<[HWPort0,HWPort5,HWPort015,HWPort0156]> { + let Latency = 19; + let NumMicroOps = 9; + let ResourceCycles = [4,3,1,1]; } -def : InstRW<[WriteVRCPPSr], (instregex "VRCPPSYr(_Int)?")>; +def: InstRW<[HWWriteResGroup133], (instregex "PCMPESTRM128rr")>; +def: InstRW<[HWWriteResGroup133], (instregex "VPCMPESTRM128rr")>; -// y,m256. -def WriteVRCPPSm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> { - let Latency = 11; - let NumMicroOps = 4; - let ResourceCycles = [2, 1, 1]; +def HWWriteResGroup134 : SchedWriteRes<[HWPort0,HWPort5,HWPort23,HWPort015,HWPort0156]> { + let Latency = 19; + let NumMicroOps = 10; + let ResourceCycles = [4,3,1,1,1]; +} +def: InstRW<[HWWriteResGroup134], (instregex "PCMPESTRM128rm")>; +def: InstRW<[HWWriteResGroup134], (instregex "VPCMPESTRM128rm")>; +def: InstRW<[HWWriteResGroup134], (instregex "SQRTPDr")>; +def: InstRW<[HWWriteResGroup134], (instregex "SQRTSDr")>; +def: InstRW<[HWWriteResGroup134], (instregex "VDIVPDrr")>; +def: InstRW<[HWWriteResGroup134], (instregex "VDIVSDrr")>; +def: InstRW<[HWWriteResGroup134], (instregex "SQRTPDm")>; +def: InstRW<[HWWriteResGroup134], (instregex "SQRTSDm")>; +def: InstRW<[HWWriteResGroup134], (instregex "VDIVPDrm")>; +def: InstRW<[HWWriteResGroup134], (instregex "VDIVSDrm")>; + +def HWWriteResGroup135 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> { + let Latency = 20; + let NumMicroOps = 10; + let ResourceCycles = [1,2,7]; } -def : InstRW<[WriteVRCPPSm], (instregex "VRCPPSYm(_Int)?")>; +def: InstRW<[HWWriteResGroup135], (instregex "MWAITrr")>; -// ROUND SS/SD PS/PD. -// v,v,i. -def WriteROUNDr : SchedWriteRes<[HWPort1]> { - let Latency = 6; +def HWWriteResGroup136 : SchedWriteRes<[HWPort0]> { + let Latency = 21; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[HWWriteResGroup136], (instregex "VSQRTPDr")>; +def: InstRW<[HWWriteResGroup136], (instregex "VSQRTSDr")>; + +def HWWriteResGroup137 : SchedWriteRes<[HWPort0,HWPort23]> { + let Latency = 21; let NumMicroOps = 2; - let ResourceCycles = [2]; + let ResourceCycles = [1,1]; } -def : InstRW<[WriteROUNDr], (instregex "(V?)ROUND(Y?)(S|P)(S|D)r(_Int)?")>; +def: InstRW<[HWWriteResGroup137], (instregex "VSQRTPDm")>; +def: InstRW<[HWWriteResGroup137], (instregex "VSQRTSDm")>; -// v,m,i. -def WriteROUNDm : SchedWriteRes<[HWPort1, HWPort23]> { - let Latency = 10; +def HWWriteResGroup138 : SchedWriteRes<[HWPort0,HWPort015]> { + let Latency = 21; let NumMicroOps = 3; - let ResourceCycles = [2, 1]; + let ResourceCycles = [2,1]; } -def : InstRW<[WriteROUNDm], (instregex "(V?)ROUND(Y?)(S|P)(S|D)m(_Int)?")>; +def: InstRW<[HWWriteResGroup138], (instregex "VDIVPSYrr")>; +def: InstRW<[HWWriteResGroup138], (instregex "VSQRTPSYr")>; -// DPPS. -// x,x,i / v,v,v,i. -def WriteDPPSr : SchedWriteRes<[HWPort0, HWPort1, HWPort5]> { - let Latency = 14; +def HWWriteResGroup139 : SchedWriteRes<[HWPort0,HWPort23,HWPort015]> { + let Latency = 21; let NumMicroOps = 4; - let ResourceCycles = [2, 1, 1]; + let ResourceCycles = [2,1,1]; } -def : InstRW<[WriteDPPSr], (instregex "(V?)DPPS(Y?)rri")>; +def: InstRW<[HWWriteResGroup139], (instregex "VDIVPSYrm")>; +def: InstRW<[HWWriteResGroup139], (instregex "VSQRTPSYm")>; -// x,m,i / v,v,m,i. -def WriteDPPSm : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort23, HWPort6]> { - let Latency = 18; - let NumMicroOps = 6; - let ResourceCycles = [2, 1, 1, 1, 1]; +def HWWriteResGroup140 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { + let Latency = 24; + let NumMicroOps = 27; + let ResourceCycles = [1,5,1,1,19]; } -def : InstRW<[WriteDPPSm, ReadAfterLd], (instregex "(V?)DPPS(Y?)rmi")>; +def: InstRW<[HWWriteResGroup140], (instregex "XSAVE64")>; -// DPPD. -// x,x,i. -def WriteDPPDr : SchedWriteRes<[HWPort0, HWPort1, HWPort5]> { - let Latency = 9; - let NumMicroOps = 3; - let ResourceCycles = [1, 1, 1]; +def HWWriteResGroup141 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { + let Latency = 25; + let NumMicroOps = 28; + let ResourceCycles = [1,6,1,1,19]; } -def : InstRW<[WriteDPPDr], (instregex "(V?)DPPDrri")>; +def: InstRW<[HWWriteResGroup141], (instregex "XSAVE")>; -// x,m,i. -def WriteDPPDm : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort23]> { - let Latency = 13; - let NumMicroOps = 4; - let ResourceCycles = [1, 1, 1, 1]; +def HWWriteResGroup142 : SchedWriteRes<[HWPort0,HWPort5,HWPort23,HWPort015]> { + let Latency = 28; + let NumMicroOps = 11; + let ResourceCycles = [2,7,1,1]; } -def : InstRW<[WriteDPPDm], (instregex "(V?)DPPDrmi")>; +def: InstRW<[HWWriteResGroup142], (instregex "AESKEYGENASSIST128rm")>; +def: InstRW<[HWWriteResGroup142], (instregex "VAESKEYGENASSIST128rm")>; -// VFMADD. -// v,v,v. -def WriteFMADDr : SchedWriteRes<[HWPort01]> { - let Latency = 5; - let NumMicroOps = 1; -} -def : InstRW<[WriteFMADDr], - (instregex - // 3p forms. - "VF(N?)M(ADD|SUB|ADDSUB|SUBADD)P(S|D)(r213|r132|r231)r(Y)?", - // 3s forms. - "VF(N?)M(ADD|SUB)S(S|D)(r132|r231|r213)r", - // 4s/4s_int forms. - "VF(N?)M(ADD|SUB)S(S|D)4rr(_REV|_Int)?", - // 4p forms. - "VF(N?)M(ADD|SUB)P(S|D)4rr(Y)?(_REV)?")>; - -// v,v,m. -def WriteFMADDm : SchedWriteRes<[HWPort01, HWPort23]> { - let Latency = 9; - let NumMicroOps = 2; - let ResourceCycles = [1, 1]; -} -def : InstRW<[WriteFMADDm], - (instregex - // 3p forms. - "VF(N?)M(ADD|SUB|ADDSUB|SUBADD)P(S|D)(r213|r132|r231)m(Y)?", - // 3s forms. - "VF(N?)M(ADD|SUB)S(S|D)(r132|r231|r213)m", - // 4s/4s_int forms. - "VF(N?)M(ADD|SUB)S(S|D)4(rm|mr)(_Int)?", - // 4p forms. - "VF(N?)M(ADD|SUB)P(S|D)4(rm|mr)(Y)?")>; - -//-- Math instructions --// - -// VSQRTPS. -// y,y. -def WriteVSQRTPSYr : SchedWriteRes<[HWPort0, HWPort15]> { - let Latency = 19; - let NumMicroOps = 3; - let ResourceCycles = [2, 1]; +def HWWriteResGroup143 : SchedWriteRes<[HWPort0,HWPort5,HWPort015]> { + let Latency = 29; + let NumMicroOps = 11; + let ResourceCycles = [2,7,2]; } -def : InstRW<[WriteVSQRTPSYr], (instregex "VSQRTPSYr")>; +def: InstRW<[HWWriteResGroup143], (instregex "AESKEYGENASSIST128rr")>; +def: InstRW<[HWWriteResGroup143], (instregex "VAESKEYGENASSIST128rr")>; -// y,m256. -def WriteVSQRTPSYm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> { - let Latency = 23; - let NumMicroOps = 4; - let ResourceCycles = [2, 1, 1]; +def HWWriteResGroup145 : SchedWriteRes<[HWPort01,HWPort15,HWPort015,HWPort0156]> { + let Latency = 31; + let NumMicroOps = 31; + let ResourceCycles = [8,1,21,1]; } -def : InstRW<[WriteVSQRTPSYm], (instregex "VSQRTPSYm")>; +def: InstRW<[HWWriteResGroup145], (instregex "MMX_EMMS")>; -// VSQRTPD. -// y,y. -def WriteVSQRTPDYr : SchedWriteRes<[HWPort0, HWPort15]> { - let Latency = 28; +def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort015]> { + let Latency = 35; let NumMicroOps = 3; - let ResourceCycles = [2, 1]; + let ResourceCycles = [2,1]; } -def : InstRW<[WriteVSQRTPDYr], (instregex "VSQRTPDYr")>; +def: InstRW<[HWWriteResGroup146], (instregex "VDIVPDYrr")>; +def: InstRW<[HWWriteResGroup146], (instregex "VSQRTPDYr")>; -// y,m256. -def WriteVSQRTPDYm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> { - let Latency = 32; +def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort23,HWPort015]> { + let Latency = 35; let NumMicroOps = 4; - let ResourceCycles = [2, 1, 1]; + let ResourceCycles = [2,1,1]; } -def : InstRW<[WriteVSQRTPDYm], (instregex "VSQRTPDYm")>; +def: InstRW<[HWWriteResGroup147], (instregex "VDIVPDYrm")>; +def: InstRW<[HWWriteResGroup147], (instregex "VSQRTPDYm")>; -// RSQRT SS/PS. -// x,x. -def WriteRSQRTr : SchedWriteRes<[HWPort0]> { - let Latency = 5; +def HWWriteResGroup148 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> { + let Latency = 35; + let NumMicroOps = 18; + let ResourceCycles = [1,1,2,3,1,1,1,8]; } -def : InstRW<[WriteRSQRTr], (instregex "(V?)RSQRT(SS|PS)r(_Int)?")>; +def: InstRW<[HWWriteResGroup148], (instregex "VMCLEARm")>; -// x,m128. -def WriteRSQRTm : SchedWriteRes<[HWPort0, HWPort23]> { - let Latency = 9; - let NumMicroOps = 2; - let ResourceCycles = [1, 1]; +def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort0156]> { + let Latency = 42; + let NumMicroOps = 22; + let ResourceCycles = [2,20]; } -def : InstRW<[WriteRSQRTm], (instregex "(V?)RSQRT(SS|PS)m(_Int)?")>; +def: InstRW<[HWWriteResGroup149], (instregex "RDTSCP")>; -// RSQRTPS 256. -// y,y. -def WriteRSQRTPSYr : SchedWriteRes<[HWPort0, HWPort15]> { - let Latency = 7; - let NumMicroOps = 3; - let ResourceCycles = [2, 1]; +def HWWriteResGroup150 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort0,HWPort0,HWPort015,HWPort0156]> { + let Latency = 56; + let NumMicroOps = 64; + let ResourceCycles = [2,2,8,1,10,2,39]; } -def : InstRW<[WriteRSQRTPSYr], (instregex "VRSQRTPSYr(_Int)?")>; +def: InstRW<[HWWriteResGroup150], (instregex "FLDENVm")>; +def: InstRW<[HWWriteResGroup150], (instregex "FLDENVm")>; -// y,m256. -def WriteRSQRTPSYm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> { - let Latency = 11; - let NumMicroOps = 4; - let ResourceCycles = [2, 1, 1]; +def HWWriteResGroup151 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort0,HWPort0,HWPort15,HWPort0156]> { + let Latency = 59; + let NumMicroOps = 88; + let ResourceCycles = [4,4,31,1,2,1,45]; } -def : InstRW<[WriteRSQRTPSYm], (instregex "VRSQRTPSYm(_Int)?")>; +def: InstRW<[HWWriteResGroup151], (instregex "FXRSTOR64")>; -//-- Logic instructions --// - -// AND, ANDN, OR, XOR PS/PD. -// x,x / v,v,v. -def : InstRW<[WriteP5], (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rr")>; -// x,m / v,v,m. -def : InstRW<[WriteP5Ld, ReadAfterLd], - (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rm")>; - -//-- Other instructions --// +def HWWriteResGroup152 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort0,HWPort0,HWPort15,HWPort0156]> { + let Latency = 59; + let NumMicroOps = 90; + let ResourceCycles = [4,2,33,1,2,1,47]; +} +def: InstRW<[HWWriteResGroup152], (instregex "FXRSTOR")>; -// VZEROUPPER. -def WriteVZEROUPPER : SchedWriteRes<[]> { - let NumMicroOps = 4; +def HWWriteResGroup153 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> { + let Latency = 75; + let NumMicroOps = 15; + let ResourceCycles = [6,3,6]; } -def : InstRW<[WriteVZEROUPPER], (instregex "VZEROUPPER")>; +def: InstRW<[HWWriteResGroup153], (instregex "FNINIT")>; -// VZEROALL. -def WriteVZEROALL : SchedWriteRes<[]> { - let NumMicroOps = 12; +def HWWriteResGroup154 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> { + let Latency = 98; + let NumMicroOps = 32; + let ResourceCycles = [7,7,3,3,1,11]; } -def : InstRW<[WriteVZEROALL], (instregex "VZEROALL")>; +def: InstRW<[HWWriteResGroup154], (instregex "DIV64r")>; -// LDMXCSR. -def WriteLDMXCSR : SchedWriteRes<[HWPort0, HWPort6, HWPort23]> { - let Latency = 6; - let NumMicroOps = 3; - let ResourceCycles = [1, 1, 1]; +def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort0,HWPort0156]> { + let Latency = 112; + let NumMicroOps = 66; + let ResourceCycles = [4,2,4,8,14,34]; } -def : InstRW<[WriteLDMXCSR], (instregex "(V)?LDMXCSR")>; +def: InstRW<[HWWriteResGroup155], (instregex "IDIV64r")>; -// STMXCSR. -def WriteSTMXCSR : SchedWriteRes<[HWPort0, HWPort4, HWPort6, HWPort237]> { - let Latency = 7; - let NumMicroOps = 4; - let ResourceCycles = [1, 1, 1, 1]; +def HWWriteResGroup156 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort0,HWPort0156]> { + let Latency = 114; + let NumMicroOps = 100; + let ResourceCycles = [9,9,11,8,1,11,21,30]; } -def : InstRW<[WriteSTMXCSR], (instregex "(V)?STMXCSR")>; +def: InstRW<[HWWriteResGroup156], (instregex "FSTENVm")>; +def: InstRW<[HWWriteResGroup156], (instregex "FSTENVm")>; } // SchedModel diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index b8ec5883152..c408f72c1ba 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -24,8 +24,8 @@ def SandyBridgeModel : SchedMachineModel { // Based on the LSD (loop-stream detector) queue size. let LoopMicroOpBufferSize = 28; - // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow - // the scheduler to assign a default model to unrecognized opcodes. + // This flag is set to allow the scheduler to assign + // a default model to unrecognized opcodes. let CompleteModel = 0; } @@ -48,6 +48,7 @@ def SBPort23 : ProcResource<2>; def SBPort4 : ProcResource<1>; // Many micro-ops are capable of issuing on multiple ports. +def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; @@ -157,31 +158,6 @@ def : WriteRes<WriteMPSADLd, [SBPort0, SBPort1, SBPort5, SBPort23]> { let ResourceCycles = [1, 1, 1, 1]; } -//////////////////////////////////////////////////////////////////////////////// -// Horizontal add/sub instructions. -//////////////////////////////////////////////////////////////////////////////// -// HADD, HSUB PS/PD -// x,x / v,v,v. -def : WriteRes<WriteFHAdd, [SBPort1]> { - let Latency = 3; -} - -// x,m / v,v,m. -def : WriteRes<WriteFHAddLd, [SBPort1, SBPort23]> { - let Latency = 7; - let ResourceCycles = [1, 1]; -} - -// PHADD|PHSUB (S) W/D. -// v <- v,v. -def : WriteRes<WritePHAdd, [SBPort15]>; - -// v <- v,m. -def : WriteRes<WritePHAddLd, [SBPort15, SBPort23]> { - let Latency = 5; - let ResourceCycles = [1, 1]; -} - // String instructions. // Packed Compare Implicit Length Strings, Return Mask def : WriteRes<WritePCmpIStrM, [SBPort015]> { @@ -272,4 +248,2282 @@ def : WriteRes<WriteNop, []>; defm : SBWriteResPair<WriteFShuffle256, SBPort0, 1>; defm : SBWriteResPair<WriteShuffle256, SBPort0, 1>; defm : SBWriteResPair<WriteVarVecShift, SBPort0, 1>; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// +// HADD, HSUB PS/PD +// x,x / v,v,v. +def : WriteRes<WriteFHAdd, [SBPort1]> { + let Latency = 3; +} + +// x,m / v,v,m. +def : WriteRes<WriteFHAddLd, [SBPort1, SBPort23]> { + let Latency = 7; + let ResourceCycles = [1, 1]; +} + +// PHADD|PHSUB (S) W/D. +// v <- v,v. +def : WriteRes<WritePHAdd, [SBPort15]>; + +// v <- v,m. +def : WriteRes<WritePHAddLd, [SBPort15, SBPort23]> { + let Latency = 5; + let ResourceCycles = [1, 1]; +} + +// Remaining SNB instrs. + +def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup0], (instregex "CVTSS2SDrr")>; +def: InstRW<[SBWriteResGroup0], (instregex "PSLLDri")>; +def: InstRW<[SBWriteResGroup0], (instregex "PSLLQri")>; +def: InstRW<[SBWriteResGroup0], (instregex "PSLLWri")>; +def: InstRW<[SBWriteResGroup0], (instregex "PSRADri")>; +def: InstRW<[SBWriteResGroup0], (instregex "PSRAWri")>; +def: InstRW<[SBWriteResGroup0], (instregex "PSRLDri")>; +def: InstRW<[SBWriteResGroup0], (instregex "PSRLQri")>; +def: InstRW<[SBWriteResGroup0], (instregex "PSRLWri")>; +def: InstRW<[SBWriteResGroup0], (instregex "VCVTSS2SDrr")>; +def: InstRW<[SBWriteResGroup0], (instregex "VPMOVMSKBrr")>; +def: InstRW<[SBWriteResGroup0], (instregex "VPSLLDri")>; +def: InstRW<[SBWriteResGroup0], (instregex "VPSLLQri")>; +def: InstRW<[SBWriteResGroup0], (instregex "VPSLLWri")>; +def: InstRW<[SBWriteResGroup0], (instregex "VPSRADri")>; +def: InstRW<[SBWriteResGroup0], (instregex "VPSRAWri")>; +def: InstRW<[SBWriteResGroup0], (instregex "VPSRLDri")>; +def: InstRW<[SBWriteResGroup0], (instregex "VPSRLQri")>; +def: InstRW<[SBWriteResGroup0], (instregex "VPSRLWri")>; +def: InstRW<[SBWriteResGroup0], (instregex "VTESTPDYrr")>; +def: InstRW<[SBWriteResGroup0], (instregex "VTESTPDrr")>; +def: InstRW<[SBWriteResGroup0], (instregex "VTESTPSYrr")>; +def: InstRW<[SBWriteResGroup0], (instregex "VTESTPSrr")>; + +def SBWriteResGroup1 : SchedWriteRes<[SBPort5]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup1], (instregex "ANDNPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "ANDNPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "ANDPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "ANDPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "FDECSTP")>; +def: InstRW<[SBWriteResGroup1], (instregex "FFREE")>; +def: InstRW<[SBWriteResGroup1], (instregex "FINCSTP")>; +def: InstRW<[SBWriteResGroup1], (instregex "FNOP")>; +def: InstRW<[SBWriteResGroup1], (instregex "INSERTPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "JMP64r")>; +def: InstRW<[SBWriteResGroup1], (instregex "MOV64toPQIrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "MOVAPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "MOVAPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "MOVDDUPrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "MOVDI2PDIrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "MOVHLPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "MOVLHPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "MOVSDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "MOVSHDUPrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "MOVSLDUPrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "MOVSSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "MOVUPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "MOVUPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "ORPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "ORPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "RETQ")>; +def: InstRW<[SBWriteResGroup1], (instregex "SHUFPDrri")>; +def: InstRW<[SBWriteResGroup1], (instregex "SHUFPSrri")>; +def: InstRW<[SBWriteResGroup1], (instregex "UNPCKHPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "UNPCKHPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "UNPCKLPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "UNPCKLPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VANDNPDYrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VANDNPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VANDNPSYrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VANDNPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VANDPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VANDPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VANDPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VEXTRACTF128rr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VGATHERQPSZrm")>; +def: InstRW<[SBWriteResGroup1], (instregex "VINSERTF128rr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VINSERTPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOV64toPQIrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOV64toPQIrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVAPDYrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVAPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVAPSYrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVAPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVDDUPYrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVDDUPrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVHLPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVHLPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVSDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVSHDUPYrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVSHDUPrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVSLDUPYrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVSLDUPrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVSSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVUPDYrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVUPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVUPSYrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VMOVUPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VORPDYrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VORPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VORPSYrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VORPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VPERMILPDri")>; +def: InstRW<[SBWriteResGroup1], (instregex "VPERMILPDrm")>; +def: InstRW<[SBWriteResGroup1], (instregex "VPERMILPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VPERMILPSri")>; +def: InstRW<[SBWriteResGroup1], (instregex "VPERMILPSrm")>; +def: InstRW<[SBWriteResGroup1], (instregex "VPERMILPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VPERMILPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VSHUFPDYrri")>; +def: InstRW<[SBWriteResGroup1], (instregex "VSHUFPDrri")>; +def: InstRW<[SBWriteResGroup1], (instregex "VSHUFPSYrri")>; +def: InstRW<[SBWriteResGroup1], (instregex "VSHUFPSrri")>; +def: InstRW<[SBWriteResGroup1], (instregex "VUNPCKHPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VUNPCKHPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VUNPCKLPDYrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VUNPCKLPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VUNPCKLPSYrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VUNPCKLPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VXORPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "VXORPSrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "XORPDrr")>; +def: InstRW<[SBWriteResGroup1], (instregex "XORPSrr")>; + +def SBWriteResGroup2 : SchedWriteRes<[SBPort01]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup2], (instregex "LEA64_32r")>; + +def SBWriteResGroup3 : SchedWriteRes<[SBPort0]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup3], (instregex "BLENDPDrri")>; +def: InstRW<[SBWriteResGroup3], (instregex "BLENDPSrri")>; +def: InstRW<[SBWriteResGroup3], (instregex "BT32ri8")>; +def: InstRW<[SBWriteResGroup3], (instregex "BT32rr")>; +def: InstRW<[SBWriteResGroup3], (instregex "BTC32ri8")>; +def: InstRW<[SBWriteResGroup3], (instregex "BTC32rr")>; +def: InstRW<[SBWriteResGroup3], (instregex "BTR32ri8")>; +def: InstRW<[SBWriteResGroup3], (instregex "BTR32rr")>; +def: InstRW<[SBWriteResGroup3], (instregex "BTS32ri8")>; +def: InstRW<[SBWriteResGroup3], (instregex "BTS32rr")>; +def: InstRW<[SBWriteResGroup3], (instregex "CDQ")>; +def: InstRW<[SBWriteResGroup3], (instregex "CQO")>; +def: InstRW<[SBWriteResGroup3], (instregex "LAHF")>; +def: InstRW<[SBWriteResGroup3], (instregex "SAHF")>; +def: InstRW<[SBWriteResGroup3], (instregex "SAR32ri")>; +def: InstRW<[SBWriteResGroup3], (instregex "SAR8ri")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETAEr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETBr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETEr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETGEr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETGr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETLEr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETLr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETNEr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETNOr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETNPr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETNSr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETOr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETPr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SETSr")>; +def: InstRW<[SBWriteResGroup3], (instregex "SHL32ri")>; +def: InstRW<[SBWriteResGroup3], (instregex "SHL64r1")>; +def: InstRW<[SBWriteResGroup3], (instregex "SHL8r1")>; +def: InstRW<[SBWriteResGroup3], (instregex "SHL8ri")>; +def: InstRW<[SBWriteResGroup3], (instregex "SHR32ri")>; +def: InstRW<[SBWriteResGroup3], (instregex "SHR8ri")>; +def: InstRW<[SBWriteResGroup3], (instregex "VBLENDPDYrri")>; +def: InstRW<[SBWriteResGroup3], (instregex "VBLENDPDrri")>; +def: InstRW<[SBWriteResGroup3], (instregex "VBLENDPSYrri")>; +def: InstRW<[SBWriteResGroup3], (instregex "VBLENDPSrri")>; +def: InstRW<[SBWriteResGroup3], (instregex "VMOVDQAYrr")>; +def: InstRW<[SBWriteResGroup3], (instregex "VMOVDQArr")>; +def: InstRW<[SBWriteResGroup3], (instregex "VMOVDQUYrr")>; +def: InstRW<[SBWriteResGroup3], (instregex "VMOVDQUrr")>; + +def SBWriteResGroup4 : SchedWriteRes<[SBPort15]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup4], (instregex "KORTESTBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "MMX_PABSBrr64")>; +def: InstRW<[SBWriteResGroup4], (instregex "MMX_PABSDrr64")>; +def: InstRW<[SBWriteResGroup4], (instregex "MMX_PABSWrr64")>; +def: InstRW<[SBWriteResGroup4], (instregex "MMX_PADDQirr")>; +def: InstRW<[SBWriteResGroup4], (instregex "MMX_PALIGNR64irr")>; +def: InstRW<[SBWriteResGroup4], (instregex "MMX_PSHUFBrr64")>; +def: InstRW<[SBWriteResGroup4], (instregex "MMX_PSIGNBrr64")>; +def: InstRW<[SBWriteResGroup4], (instregex "MMX_PSIGNDrr64")>; +def: InstRW<[SBWriteResGroup4], (instregex "MMX_PSIGNWrr64")>; +def: InstRW<[SBWriteResGroup4], (instregex "PABSBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PABSDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PABSWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PACKSSDWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PACKSSWBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PACKUSDWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PACKUSWBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PADDBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PADDDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PADDQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PADDSBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PADDSWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PADDUSBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PADDUSWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PADDWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PALIGNRrri")>; +def: InstRW<[SBWriteResGroup4], (instregex "PAVGBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PAVGWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PBLENDWrri")>; +def: InstRW<[SBWriteResGroup4], (instregex "PCMPEQBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PCMPEQDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PCMPEQQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PCMPEQWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PCMPGTBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PCMPGTDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PCMPGTWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMAXSBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMAXSDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMAXSWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMAXUBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMAXUDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMAXUWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMINSBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMINSDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMINSWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMINUBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMINUDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMINUWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMOVSXBDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMOVSXBQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMOVSXBWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMOVSXDQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMOVSXWDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMOVSXWQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMOVZXBDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMOVZXBQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMOVZXBWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMOVZXDQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMOVZXWDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PMOVZXWQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSHUFBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSHUFDri")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSHUFHWri")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSHUFLWri")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSIGNBrr128")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSIGNDrr128")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSIGNWrr128")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSLLDQri")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSRLDQri")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSUBBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSUBDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSUBQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSUBSBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSUBSWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSUBUSBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSUBUSWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PSUBWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PUNPCKHBWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PUNPCKHDQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PUNPCKHQDQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PUNPCKHWDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PUNPCKLBWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PUNPCKLDQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PUNPCKLQDQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "PUNPCKLWDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VMASKMOVPSYrm")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPABSBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPABSDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPABSWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPACKSSDWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPACKSSWBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPACKUSDWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPACKUSWBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPADDBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPADDDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPADDQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPADDUSBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPADDUSWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPALIGNRrri")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPAVGBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPAVGWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPBLENDWrri")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPCMPEQBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPCMPEQDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPCMPEQWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPCMPGTBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPCMPGTDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPCMPGTWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMAXSBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMAXSDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMAXSWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMAXUBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMAXUDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMAXUWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMINSBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMINSDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMINSWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMINUBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMINUDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMINUWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMOVSXBDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMOVSXBQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMOVSXBWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMOVSXDQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMOVSXWDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMOVSXWQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMOVZXBDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMOVZXBQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMOVZXBWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMOVZXDQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMOVZXWDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPMOVZXWQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSHUFBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSHUFDri")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSHUFLWri")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSIGNBrr128")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSIGNDrr128")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSIGNWrr128")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSLLDQri")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSRLDQri")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSUBBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSUBDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSUBQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSUBSBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSUBSWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSUBUSBrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSUBUSWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPSUBWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPUNPCKHBWrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPUNPCKHDQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPUNPCKHWDrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPUNPCKLDQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPUNPCKLQDQrr")>; +def: InstRW<[SBWriteResGroup4], (instregex "VPUNPCKLWDrr")>; + +def SBWriteResGroup5 : SchedWriteRes<[SBPort015]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup5], (instregex "ADD32ri8")>; +def: InstRW<[SBWriteResGroup5], (instregex "ADD32rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "ADD8ri")>; +def: InstRW<[SBWriteResGroup5], (instregex "ADD8rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "AND32ri")>; +def: InstRW<[SBWriteResGroup5], (instregex "AND64ri8")>; +def: InstRW<[SBWriteResGroup5], (instregex "AND64rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "AND8ri")>; +def: InstRW<[SBWriteResGroup5], (instregex "AND8rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "CBW")>; +def: InstRW<[SBWriteResGroup5], (instregex "CMC")>; +def: InstRW<[SBWriteResGroup5], (instregex "CMP16ri8")>; +def: InstRW<[SBWriteResGroup5], (instregex "CMP32i32")>; +def: InstRW<[SBWriteResGroup5], (instregex "CMP64rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "CMP8ri")>; +def: InstRW<[SBWriteResGroup5], (instregex "CMP8rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "CWDE")>; +def: InstRW<[SBWriteResGroup5], (instregex "DEC64r")>; +def: InstRW<[SBWriteResGroup5], (instregex "DEC8r")>; +def: InstRW<[SBWriteResGroup5], (instregex "INC64r")>; +def: InstRW<[SBWriteResGroup5], (instregex "INC8r")>; +def: InstRW<[SBWriteResGroup5], (instregex "MMX_MOVD64from64rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "MMX_MOVQ2DQrr")>; +def: InstRW<[SBWriteResGroup5], (instregex "MOV32rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "MOV8ri")>; +def: InstRW<[SBWriteResGroup5], (instregex "MOV8rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "MOVDQArr")>; +def: InstRW<[SBWriteResGroup5], (instregex "MOVDQUrr")>; +def: InstRW<[SBWriteResGroup5], (instregex "MOVPQI2QIrr")>; +def: InstRW<[SBWriteResGroup5], (instregex "MOVSX32rr16")>; +def: InstRW<[SBWriteResGroup5], (instregex "MOVSX32rr8")>; +def: InstRW<[SBWriteResGroup5], (instregex "MOVZX32rr16")>; +def: InstRW<[SBWriteResGroup5], (instregex "MOVZX32rr8")>; +def: InstRW<[SBWriteResGroup5], (instregex "NEG64r")>; +def: InstRW<[SBWriteResGroup5], (instregex "NEG8r")>; +def: InstRW<[SBWriteResGroup5], (instregex "NOT64r")>; +def: InstRW<[SBWriteResGroup5], (instregex "NOT8r")>; +def: InstRW<[SBWriteResGroup5], (instregex "OR64ri8")>; +def: InstRW<[SBWriteResGroup5], (instregex "OR64rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "OR8ri")>; +def: InstRW<[SBWriteResGroup5], (instregex "OR8rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "PANDNrr")>; +def: InstRW<[SBWriteResGroup5], (instregex "PANDrr")>; +def: InstRW<[SBWriteResGroup5], (instregex "PORrr")>; +def: InstRW<[SBWriteResGroup5], (instregex "PXORrr")>; +def: InstRW<[SBWriteResGroup5], (instregex "STC")>; +def: InstRW<[SBWriteResGroup5], (instregex "SUB64ri8")>; +def: InstRW<[SBWriteResGroup5], (instregex "SUB64rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "SUB8ri")>; +def: InstRW<[SBWriteResGroup5], (instregex "SUB8rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "TEST64rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "TEST8ri")>; +def: InstRW<[SBWriteResGroup5], (instregex "TEST8rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "VMOVPQI2QIrr")>; +def: InstRW<[SBWriteResGroup5], (instregex "VMOVZPQILo2PQIrr")>; +def: InstRW<[SBWriteResGroup5], (instregex "VPANDNrr")>; +def: InstRW<[SBWriteResGroup5], (instregex "VPANDrr")>; +def: InstRW<[SBWriteResGroup5], (instregex "VPORrr")>; +def: InstRW<[SBWriteResGroup5], (instregex "VPXORrr")>; +def: InstRW<[SBWriteResGroup5], (instregex "XOR32rr")>; +def: InstRW<[SBWriteResGroup5], (instregex "XOR64ri8")>; +def: InstRW<[SBWriteResGroup5], (instregex "XOR8ri")>; +def: InstRW<[SBWriteResGroup5], (instregex "XOR8rr")>; + +def SBWriteResGroup6 : SchedWriteRes<[SBPort0]> { + let Latency = 2; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup6], (instregex "MOVMSKPDrr")>; +def: InstRW<[SBWriteResGroup6], (instregex "MOVMSKPSrr")>; +def: InstRW<[SBWriteResGroup6], (instregex "MOVPDI2DIrr")>; +def: InstRW<[SBWriteResGroup6], (instregex "MOVPQIto64rr")>; +def: InstRW<[SBWriteResGroup6], (instregex "PMOVMSKBrr")>; +def: InstRW<[SBWriteResGroup6], (instregex "VMOVMSKPDYrr")>; +def: InstRW<[SBWriteResGroup6], (instregex "VMOVMSKPDrr")>; +def: InstRW<[SBWriteResGroup6], (instregex "VMOVMSKPSrr")>; +def: InstRW<[SBWriteResGroup6], (instregex "VMOVPDI2DIrr")>; +def: InstRW<[SBWriteResGroup6], (instregex "VMOVPQIto64rr")>; + +def SBWriteResGroup8 : SchedWriteRes<[SBPort0]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SBWriteResGroup8], (instregex "BLENDVPDrr0")>; +def: InstRW<[SBWriteResGroup8], (instregex "BLENDVPSrr0")>; +def: InstRW<[SBWriteResGroup8], (instregex "ROL32ri")>; +def: InstRW<[SBWriteResGroup8], (instregex "ROL8ri")>; +def: InstRW<[SBWriteResGroup8], (instregex "ROR32ri")>; +def: InstRW<[SBWriteResGroup8], (instregex "ROR8ri")>; +def: InstRW<[SBWriteResGroup8], (instregex "SETAr")>; +def: InstRW<[SBWriteResGroup8], (instregex "SETBEr")>; +def: InstRW<[SBWriteResGroup8], (instregex "VBLENDVPDYrr")>; +def: InstRW<[SBWriteResGroup8], (instregex "VBLENDVPDrr")>; +def: InstRW<[SBWriteResGroup8], (instregex "VBLENDVPSYrr")>; +def: InstRW<[SBWriteResGroup8], (instregex "VBLENDVPSrr")>; + +def SBWriteResGroup9 : SchedWriteRes<[SBPort15]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SBWriteResGroup9], (instregex "VPBLENDVBrr")>; + +def SBWriteResGroup10 : SchedWriteRes<[SBPort015]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SBWriteResGroup10], (instregex "SCASB")>; +def: InstRW<[SBWriteResGroup10], (instregex "SCASL")>; +def: InstRW<[SBWriteResGroup10], (instregex "SCASQ")>; +def: InstRW<[SBWriteResGroup10], (instregex "SCASW")>; + +def SBWriteResGroup11 : SchedWriteRes<[SBPort0,SBPort1]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup11], (instregex "COMISDrr")>; +def: InstRW<[SBWriteResGroup11], (instregex "COMISSrr")>; +def: InstRW<[SBWriteResGroup11], (instregex "UCOMISDrr")>; +def: InstRW<[SBWriteResGroup11], (instregex "UCOMISSrr")>; +def: InstRW<[SBWriteResGroup11], (instregex "VCOMISDrr")>; +def: InstRW<[SBWriteResGroup11], (instregex "VCOMISSrr")>; +def: InstRW<[SBWriteResGroup11], (instregex "VUCOMISDrr")>; +def: InstRW<[SBWriteResGroup11], (instregex "VUCOMISSrr")>; + +def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort5]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup12], (instregex "CVTPS2PDrr")>; +def: InstRW<[SBWriteResGroup12], (instregex "PTESTrr")>; +def: InstRW<[SBWriteResGroup12], (instregex "VCVTPS2PDYrr")>; +def: InstRW<[SBWriteResGroup12], (instregex "VCVTPS2PDrr")>; +def: InstRW<[SBWriteResGroup12], (instregex "VPTESTYrr")>; +def: InstRW<[SBWriteResGroup12], (instregex "VPTESTrr")>; + +def SBWriteResGroup13 : SchedWriteRes<[SBPort0,SBPort15]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup13], (instregex "PSLLDrr")>; +def: InstRW<[SBWriteResGroup13], (instregex "PSLLQrr")>; +def: InstRW<[SBWriteResGroup13], (instregex "PSLLWrr")>; +def: InstRW<[SBWriteResGroup13], (instregex "PSRADrr")>; +def: InstRW<[SBWriteResGroup13], (instregex "PSRAWrr")>; +def: InstRW<[SBWriteResGroup13], (instregex "PSRLDrr")>; +def: InstRW<[SBWriteResGroup13], (instregex "PSRLQrr")>; +def: InstRW<[SBWriteResGroup13], (instregex "PSRLWrr")>; +def: InstRW<[SBWriteResGroup13], (instregex "VPSRADrr")>; +def: InstRW<[SBWriteResGroup13], (instregex "VPSRAWrr")>; +def: InstRW<[SBWriteResGroup13], (instregex "VPSRLDrr")>; +def: InstRW<[SBWriteResGroup13], (instregex "VPSRLQrr")>; +def: InstRW<[SBWriteResGroup13], (instregex "VPSRLWrr")>; + +def SBWriteResGroup14 : SchedWriteRes<[SBPort1,SBPort0]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup14], (instregex "BSWAP32r")>; + +def SBWriteResGroup15 : SchedWriteRes<[SBPort5,SBPort15]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup15], (instregex "PINSRBrr")>; +def: InstRW<[SBWriteResGroup15], (instregex "PINSRDrr")>; +def: InstRW<[SBWriteResGroup15], (instregex "PINSRQrr")>; +def: InstRW<[SBWriteResGroup15], (instregex "PINSRWrri")>; +def: InstRW<[SBWriteResGroup15], (instregex "VPINSRBrr")>; +def: InstRW<[SBWriteResGroup15], (instregex "VPINSRDrr")>; +def: InstRW<[SBWriteResGroup15], (instregex "VPINSRQrr")>; +def: InstRW<[SBWriteResGroup15], (instregex "VPINSRWrri")>; + +def SBWriteResGroup16 : SchedWriteRes<[SBPort5,SBPort015]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup16], (instregex "MMX_MOVDQ2Qrr")>; + +def SBWriteResGroup17 : SchedWriteRes<[SBPort0,SBPort015]> { + let Latency = 2; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup17], (instregex "ADC64ri8")>; +def: InstRW<[SBWriteResGroup17], (instregex "ADC64rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "ADC8ri")>; +def: InstRW<[SBWriteResGroup17], (instregex "ADC8rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVAE32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVB32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVE32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVG32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVGE32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVL32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVLE32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVNE32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVNO32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVNP32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVNS32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVO32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVP32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "CMOVS32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "SBB32rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "SBB64ri8")>; +def: InstRW<[SBWriteResGroup17], (instregex "SBB8ri")>; +def: InstRW<[SBWriteResGroup17], (instregex "SBB8rr")>; +def: InstRW<[SBWriteResGroup17], (instregex "SHLD32rri8")>; +def: InstRW<[SBWriteResGroup17], (instregex "SHRD32rri8")>; + +def SBWriteResGroup18 : SchedWriteRes<[SBPort0]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup18], (instregex "MMX_PMADDUBSWrr64")>; +def: InstRW<[SBWriteResGroup18], (instregex "MMX_PMULHRSWrr64")>; +def: InstRW<[SBWriteResGroup18], (instregex "MMX_PMULUDQirr")>; +def: InstRW<[SBWriteResGroup18], (instregex "PMADDUBSWrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "PMADDWDrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "PMULDQrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "PMULHRSWrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "PMULHUWrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "PMULHWrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "PMULLDrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "PMULLWrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "PMULUDQrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "PSADBWrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "VMOVMSKPSYrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "VPMADDUBSWrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "VPMADDWDrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "VPMULDQrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "VPMULHRSWrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "VPMULHWrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "VPMULLDrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "VPMULLWrr")>; +def: InstRW<[SBWriteResGroup18], (instregex "VPSADBWrr")>; + +def SBWriteResGroup19 : SchedWriteRes<[SBPort1]> { + let Latency = 3; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup19], (instregex "ADDPDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "ADDPSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "ADDSDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "ADDSSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "ADDSUBPDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "ADDSUBPSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "BSF32rr")>; +def: InstRW<[SBWriteResGroup19], (instregex "BSR32rr")>; +def: InstRW<[SBWriteResGroup19], (instregex "CMPPDrri")>; +def: InstRW<[SBWriteResGroup19], (instregex "CMPPSrri")>; +def: InstRW<[SBWriteResGroup19], (instregex "CMPSDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "CMPSSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "CRC32r32r32")>; +def: InstRW<[SBWriteResGroup19], (instregex "CRC32r32r8")>; +def: InstRW<[SBWriteResGroup19], (instregex "CVTDQ2PSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "CVTPS2DQrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "CVTTPS2DQrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "MAXPDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "MAXPSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "MAXSDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "MAXSSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "MINPDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "MINPSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "MINSDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "MINSSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "MMX_CVTPI2PSirr")>; +def: InstRW<[SBWriteResGroup19], (instregex "MMX_CVTPS2PIirr")>; +def: InstRW<[SBWriteResGroup19], (instregex "MMX_CVTTPS2PIirr")>; +def: InstRW<[SBWriteResGroup19], (instregex "MUL8r")>; +def: InstRW<[SBWriteResGroup19], (instregex "POPCNT32rr")>; +def: InstRW<[SBWriteResGroup19], (instregex "ROUNDPDr")>; +def: InstRW<[SBWriteResGroup19], (instregex "ROUNDPSr")>; +def: InstRW<[SBWriteResGroup19], (instregex "ROUNDSDr")>; +def: InstRW<[SBWriteResGroup19], (instregex "ROUNDSSr")>; +def: InstRW<[SBWriteResGroup19], (instregex "SUBPDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "SUBPSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "SUBSDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "SUBSSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VADDPDYrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VADDPDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VADDPSYrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VADDPSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VADDSDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VADDSSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VADDSUBPDYrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VADDSUBPDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VADDSUBPSYrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VADDSUBPSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VBROADCASTF128")>; +def: InstRW<[SBWriteResGroup19], (instregex "VCMPPDYrri")>; +def: InstRW<[SBWriteResGroup19], (instregex "VCMPPDrri")>; +def: InstRW<[SBWriteResGroup19], (instregex "VCMPPSYrri")>; +def: InstRW<[SBWriteResGroup19], (instregex "VCMPPSrri")>; +def: InstRW<[SBWriteResGroup19], (instregex "VCMPSDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VCMPSSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VCVTDQ2PSYrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VCVTDQ2PSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VCVTPS2DQYrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VCVTPS2DQrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VCVTTPS2DQrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VMAXPDYrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VMAXPDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VMAXPSYrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VMAXPSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VMAXSDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VMAXSSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VMINPDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VMINPSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VMINSDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VMINSSrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VPBROADCASTMB2QZrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VROUNDPDr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VROUNDPSr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VROUNDSDr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VSUBPDYrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VSUBPDrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VSUBPSYrr")>; +def: InstRW<[SBWriteResGroup19], (instregex "VSUBPSrr")>; + +def SBWriteResGroup20 : SchedWriteRes<[SBPort0,SBPort5]> { + let Latency = 3; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup20], (instregex "EXTRACTPSrr")>; +def: InstRW<[SBWriteResGroup20], (instregex "VEXTRACTPSrr")>; + +def SBWriteResGroup21 : SchedWriteRes<[SBPort0,SBPort15]> { + let Latency = 3; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup21], (instregex "PEXTRBrr")>; +def: InstRW<[SBWriteResGroup21], (instregex "PEXTRDrr")>; +def: InstRW<[SBWriteResGroup21], (instregex "PEXTRQrr")>; +def: InstRW<[SBWriteResGroup21], (instregex "PEXTRWri")>; +def: InstRW<[SBWriteResGroup21], (instregex "VPEXTRBrr")>; +def: InstRW<[SBWriteResGroup21], (instregex "VPEXTRDrr")>; +def: InstRW<[SBWriteResGroup21], (instregex "VPEXTRQrr")>; +def: InstRW<[SBWriteResGroup21], (instregex "VPEXTRWri")>; +def: InstRW<[SBWriteResGroup21], (instregex "SHL64rCL")>; +def: InstRW<[SBWriteResGroup21], (instregex "SHL8rCL")>; + +def SBWriteResGroup22 : SchedWriteRes<[SBPort15]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SBWriteResGroup22], (instregex "MMX_PHADDSWrr64")>; +def: InstRW<[SBWriteResGroup22], (instregex "MMX_PHADDWrr64")>; +def: InstRW<[SBWriteResGroup22], (instregex "MMX_PHADDrr64")>; +def: InstRW<[SBWriteResGroup22], (instregex "MMX_PHSUBDrr64")>; +def: InstRW<[SBWriteResGroup22], (instregex "MMX_PHSUBSWrr64")>; +def: InstRW<[SBWriteResGroup22], (instregex "MMX_PHSUBWrr64")>; +def: InstRW<[SBWriteResGroup22], (instregex "PHADDDrr")>; +def: InstRW<[SBWriteResGroup22], (instregex "PHADDSWrr128")>; +def: InstRW<[SBWriteResGroup22], (instregex "PHADDWrr")>; +def: InstRW<[SBWriteResGroup22], (instregex "PHSUBDrr")>; +def: InstRW<[SBWriteResGroup22], (instregex "PHSUBSWrr128")>; +def: InstRW<[SBWriteResGroup22], (instregex "PHSUBWrr")>; +def: InstRW<[SBWriteResGroup22], (instregex "VPHADDDrr")>; +def: InstRW<[SBWriteResGroup22], (instregex "VPHADDSWrr128")>; +def: InstRW<[SBWriteResGroup22], (instregex "VPHADDWrr")>; +def: InstRW<[SBWriteResGroup22], (instregex "VPHSUBDrr")>; +def: InstRW<[SBWriteResGroup22], (instregex "VPHSUBSWrr128")>; +def: InstRW<[SBWriteResGroup22], (instregex "VPHSUBWrr")>; + +def SBWriteResGroup23 : SchedWriteRes<[SBPort015]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SBWriteResGroup23], (instregex "LEAVE64")>; +def: InstRW<[SBWriteResGroup23], (instregex "XADD32rr")>; +def: InstRW<[SBWriteResGroup23], (instregex "XADD8rr")>; + +def SBWriteResGroup24 : SchedWriteRes<[SBPort0,SBPort015]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SBWriteResGroup24], (instregex "CMOVA32rr")>; +def: InstRW<[SBWriteResGroup24], (instregex "CMOVBE32rr")>; + +def SBWriteResGroup25 : SchedWriteRes<[SBPort0,SBPort1]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup25], (instregex "MUL64r")>; + +def SBWriteResGroup26 : SchedWriteRes<[SBPort1,SBPort5]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup26], (instregex "CVTDQ2PDrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "CVTPD2DQrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "CVTPD2PSrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "CVTSD2SSrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "CVTSI2SD64rr")>; +def: InstRW<[SBWriteResGroup26], (instregex "CVTSI2SDrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "CVTTPD2DQrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "MMX_CVTPD2PIirr")>; +def: InstRW<[SBWriteResGroup26], (instregex "MMX_CVTPI2PDirr")>; +def: InstRW<[SBWriteResGroup26], (instregex "MMX_CVTTPD2PIirr")>; +def: InstRW<[SBWriteResGroup26], (instregex "VCVTDQ2PDYrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "VCVTDQ2PDrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "VCVTPD2DQYrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "VCVTPD2DQrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "VCVTPD2PSYrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "VCVTPD2PSrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "VCVTSI2SD64rr")>; +def: InstRW<[SBWriteResGroup26], (instregex "VCVTSI2SDrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "VCVTTPD2DQYrr")>; +def: InstRW<[SBWriteResGroup26], (instregex "VCVTTPD2DQrr")>; + +def SBWriteResGroup27 : SchedWriteRes<[SBPort1,SBPort015]> { + let Latency = 4; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup27], (instregex "MOV64sr")>; +def: InstRW<[SBWriteResGroup27], (instregex "PAUSE")>; + +def SBWriteResGroup28 : SchedWriteRes<[SBPort0]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup28], (instregex "MULPDrr")>; +def: InstRW<[SBWriteResGroup28], (instregex "MULPSrr")>; +def: InstRW<[SBWriteResGroup28], (instregex "MULSDrr")>; +def: InstRW<[SBWriteResGroup28], (instregex "MULSSrr")>; +def: InstRW<[SBWriteResGroup28], (instregex "PCMPGTQrr")>; +def: InstRW<[SBWriteResGroup28], (instregex "PHMINPOSUWrr128")>; +def: InstRW<[SBWriteResGroup28], (instregex "RCPPSr")>; +def: InstRW<[SBWriteResGroup28], (instregex "RCPSSr")>; +def: InstRW<[SBWriteResGroup28], (instregex "RSQRTPSr")>; +def: InstRW<[SBWriteResGroup28], (instregex "RSQRTSSr")>; +def: InstRW<[SBWriteResGroup28], (instregex "VMULPDYrr")>; +def: InstRW<[SBWriteResGroup28], (instregex "VMULPDrr")>; +def: InstRW<[SBWriteResGroup28], (instregex "VMULPSYrr")>; +def: InstRW<[SBWriteResGroup28], (instregex "VMULPSrr")>; +def: InstRW<[SBWriteResGroup28], (instregex "VMULSDrr")>; +def: InstRW<[SBWriteResGroup28], (instregex "VMULSSrr")>; +def: InstRW<[SBWriteResGroup28], (instregex "VPCMPGTQrr")>; +def: InstRW<[SBWriteResGroup28], (instregex "VPHMINPOSUWrr128")>; +def: InstRW<[SBWriteResGroup28], (instregex "VRSQRTPSr")>; +def: InstRW<[SBWriteResGroup28], (instregex "VRSQRTSSr")>; + +def SBWriteResGroup29 : SchedWriteRes<[SBPort23]> { + let Latency = 5; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup29], (instregex "MOV32rm")>; +def: InstRW<[SBWriteResGroup29], (instregex "MOV8rm")>; +def: InstRW<[SBWriteResGroup29], (instregex "MOVSX32rm16")>; +def: InstRW<[SBWriteResGroup29], (instregex "MOVSX32rm8")>; +def: InstRW<[SBWriteResGroup29], (instregex "MOVZX32rm16")>; +def: InstRW<[SBWriteResGroup29], (instregex "MOVZX32rm8")>; +def: InstRW<[SBWriteResGroup29], (instregex "PREFETCH")>; + +def SBWriteResGroup30 : SchedWriteRes<[SBPort0,SBPort1]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup30], (instregex "CVTSD2SI64rr")>; +def: InstRW<[SBWriteResGroup30], (instregex "CVTSD2SIrr")>; +def: InstRW<[SBWriteResGroup30], (instregex "CVTSS2SI64rr")>; +def: InstRW<[SBWriteResGroup30], (instregex "CVTSS2SIrr")>; +def: InstRW<[SBWriteResGroup30], (instregex "CVTTSD2SI64rr")>; +def: InstRW<[SBWriteResGroup30], (instregex "CVTTSD2SIrr")>; +def: InstRW<[SBWriteResGroup30], (instregex "CVTTSS2SI64rr")>; +def: InstRW<[SBWriteResGroup30], (instregex "CVTTSS2SIrr")>; +def: InstRW<[SBWriteResGroup30], (instregex "VCVTSD2SI64rr")>; +def: InstRW<[SBWriteResGroup30], (instregex "VCVTSS2SI64rr")>; +def: InstRW<[SBWriteResGroup30], (instregex "VCVTSS2SIrr")>; +def: InstRW<[SBWriteResGroup30], (instregex "VCVTTSD2SI64rr")>; +def: InstRW<[SBWriteResGroup30], (instregex "VCVTTSD2SIrr")>; +def: InstRW<[SBWriteResGroup30], (instregex "VCVTTSS2SI64rr")>; +def: InstRW<[SBWriteResGroup30], (instregex "VCVTTSS2SIrr")>; + +def SBWriteResGroup31 : SchedWriteRes<[SBPort4,SBPort23]> { + let Latency = 5; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup31], (instregex "MOV64mr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOV8mr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVAPDmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVAPSmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVDQAmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVDQUmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVHPDmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVHPSmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVLPDmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVLPSmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVNTDQmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVNTI_64mr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVNTImr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVNTPDmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVNTPSmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVPDI2DImr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVPQI2QImr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVPQIto64mr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVSSmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVUPDmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "MOVUPSmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "PUSH64i8")>; +def: InstRW<[SBWriteResGroup31], (instregex "PUSH64r")>; +def: InstRW<[SBWriteResGroup31], (instregex "VEXTRACTF128mr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVAPDYmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVAPDmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVAPSYmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVAPSmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVDQAYmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVDQAmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVDQUYmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVDQUmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVHPDmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVHPSmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVLPDmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVLPSmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVNTDQYmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVNTDQmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVNTPDYmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVNTPDmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVNTPSYmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVNTPSmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVPDI2DImr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVPQI2QImr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVPQIto64mr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVSDmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVSSmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVUPDYmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVUPDmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVUPSYmr")>; +def: InstRW<[SBWriteResGroup31], (instregex "VMOVUPSmr")>; + +def SBWriteResGroup32 : SchedWriteRes<[SBPort0,SBPort15]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup32], (instregex "MPSADBWrri")>; +def: InstRW<[SBWriteResGroup32], (instregex "VMPSADBWrri")>; + +def SBWriteResGroup33 : SchedWriteRes<[SBPort1,SBPort5]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup33], (instregex "CLI")>; +def: InstRW<[SBWriteResGroup33], (instregex "CVTSI2SS64rr")>; +def: InstRW<[SBWriteResGroup33], (instregex "CVTSI2SSrr")>; +def: InstRW<[SBWriteResGroup33], (instregex "HADDPDrr")>; +def: InstRW<[SBWriteResGroup33], (instregex "HADDPSrr")>; +def: InstRW<[SBWriteResGroup33], (instregex "HSUBPDrr")>; +def: InstRW<[SBWriteResGroup33], (instregex "HSUBPSrr")>; +def: InstRW<[SBWriteResGroup33], (instregex "VCVTSI2SS64rr")>; +def: InstRW<[SBWriteResGroup33], (instregex "VCVTSI2SSrr")>; +def: InstRW<[SBWriteResGroup33], (instregex "VHADDPDrr")>; +def: InstRW<[SBWriteResGroup33], (instregex "VHADDPSYrr")>; +def: InstRW<[SBWriteResGroup33], (instregex "VHADDPSrr")>; +def: InstRW<[SBWriteResGroup33], (instregex "VHSUBPDYrr")>; +def: InstRW<[SBWriteResGroup33], (instregex "VHSUBPDrr")>; +def: InstRW<[SBWriteResGroup33], (instregex "VHSUBPSYrr")>; +def: InstRW<[SBWriteResGroup33], (instregex "VHSUBPSrr")>; + +def SBWriteResGroup34 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup34], (instregex "CALL64r")>; +def: InstRW<[SBWriteResGroup34], (instregex "EXTRACTPSmr")>; +def: InstRW<[SBWriteResGroup34], (instregex "VEXTRACTPSmr")>; + +def SBWriteResGroup35 : SchedWriteRes<[SBPort4,SBPort01,SBPort23]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup35], (instregex "VMASKMOVPDYrm")>; +def: InstRW<[SBWriteResGroup35], (instregex "VMASKMOVPDmr")>; +def: InstRW<[SBWriteResGroup35], (instregex "VMASKMOVPSmr")>; + +def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup36], (instregex "SETAEm")>; +def: InstRW<[SBWriteResGroup36], (instregex "SETBm")>; +def: InstRW<[SBWriteResGroup36], (instregex "SETEm")>; +def: InstRW<[SBWriteResGroup36], (instregex "SETGEm")>; +def: InstRW<[SBWriteResGroup36], (instregex "SETGm")>; +def: InstRW<[SBWriteResGroup36], (instregex "SETLEm")>; +def: InstRW<[SBWriteResGroup36], (instregex "SETLm")>; +def: InstRW<[SBWriteResGroup36], (instregex "SETNEm")>; +def: InstRW<[SBWriteResGroup36], (instregex "SETNOm")>; +def: InstRW<[SBWriteResGroup36], (instregex "SETNPm")>; +def: InstRW<[SBWriteResGroup36], (instregex "SETNSm")>; +def: InstRW<[SBWriteResGroup36], (instregex "SETOm")>; +def: InstRW<[SBWriteResGroup36], (instregex "SETPm")>; +def: InstRW<[SBWriteResGroup36], (instregex "SETSm")>; + +def SBWriteResGroup37 : SchedWriteRes<[SBPort4,SBPort23,SBPort15]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup37], (instregex "PEXTRBmr")>; +def: InstRW<[SBWriteResGroup37], (instregex "VPEXTRBmr")>; +def: InstRW<[SBWriteResGroup37], (instregex "VPEXTRDmr")>; +def: InstRW<[SBWriteResGroup37], (instregex "VPEXTRWmr")>; + +def SBWriteResGroup38 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { + let Latency = 5; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup38], (instregex "MOV8mi")>; +def: InstRW<[SBWriteResGroup38], (instregex "STOSB")>; +def: InstRW<[SBWriteResGroup38], (instregex "STOSL")>; +def: InstRW<[SBWriteResGroup38], (instregex "STOSQ")>; +def: InstRW<[SBWriteResGroup38], (instregex "STOSW")>; + +def SBWriteResGroup39 : SchedWriteRes<[SBPort5,SBPort015]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SBWriteResGroup39], (instregex "FNINIT")>; + +def SBWriteResGroup40 : SchedWriteRes<[SBPort0,SBPort015]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SBWriteResGroup40], (instregex "CMPXCHG32rr")>; +def: InstRW<[SBWriteResGroup40], (instregex "CMPXCHG8rr")>; + +def SBWriteResGroup41 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup41], (instregex "SETAm")>; +def: InstRW<[SBWriteResGroup41], (instregex "SETBEm")>; + +def SBWriteResGroup42 : SchedWriteRes<[SBPort0,SBPort4,SBPort5,SBPort23]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SBWriteResGroup42], (instregex "LDMXCSR")>; +def: InstRW<[SBWriteResGroup42], (instregex "STMXCSR")>; +def: InstRW<[SBWriteResGroup42], (instregex "VLDMXCSR")>; +def: InstRW<[SBWriteResGroup42], (instregex "VSTMXCSR")>; + +def SBWriteResGroup43 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SBWriteResGroup43], (instregex "PEXTRDmr")>; +def: InstRW<[SBWriteResGroup43], (instregex "PEXTRQmr")>; +def: InstRW<[SBWriteResGroup43], (instregex "VPEXTRQmr")>; +def: InstRW<[SBWriteResGroup43], (instregex "PUSHF16")>; +def: InstRW<[SBWriteResGroup43], (instregex "PUSHF64")>; + +def SBWriteResGroup44 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { + let Latency = 5; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SBWriteResGroup44], (instregex "CLFLUSH")>; + +def SBWriteResGroup45 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { + let Latency = 5; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SBWriteResGroup45], (instregex "FXRSTOR")>; + +def SBWriteResGroup46 : SchedWriteRes<[SBPort23]> { + let Latency = 6; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup46], (instregex "LDDQUrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MMX_MOVD64from64rm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MOV64toPQIrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MOVAPDrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MOVAPSrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MOVDDUPrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MOVDI2PDIrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MOVDQArm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MOVDQUrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MOVNTDQArm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MOVSHDUPrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MOVSLDUPrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MOVSSrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MOVUPDrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "MOVUPSrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "POP64r")>; +def: InstRW<[SBWriteResGroup46], (instregex "VBROADCASTSSrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VLDDQUYrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VLDDQUrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOV64toPQIrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVAPDrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVAPSrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVDDUPrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVDI2PDIrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVDQArm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVDQUrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVNTDQArm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVQI2PQIrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVSDrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVSHDUPrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVSLDUPrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVSSrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVUPDrm")>; +def: InstRW<[SBWriteResGroup46], (instregex "VMOVUPSrm")>; + +def SBWriteResGroup47 : SchedWriteRes<[SBPort5,SBPort23]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup47], (instregex "JMP64m")>; +def: InstRW<[SBWriteResGroup47], (instregex "MOV64sm")>; + +def SBWriteResGroup48 : SchedWriteRes<[SBPort23,SBPort0]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup48], (instregex "BT64mi8")>; + +def SBWriteResGroup49 : SchedWriteRes<[SBPort23,SBPort15]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup49], (instregex "MMX_PABSBrm64")>; +def: InstRW<[SBWriteResGroup49], (instregex "MMX_PABSDrm64")>; +def: InstRW<[SBWriteResGroup49], (instregex "MMX_PABSWrm64")>; +def: InstRW<[SBWriteResGroup49], (instregex "MMX_PALIGNR64irm")>; +def: InstRW<[SBWriteResGroup49], (instregex "MMX_PSHUFBrm64")>; +def: InstRW<[SBWriteResGroup49], (instregex "MMX_PSIGNBrm64")>; +def: InstRW<[SBWriteResGroup49], (instregex "MMX_PSIGNDrm64")>; +def: InstRW<[SBWriteResGroup49], (instregex "MMX_PSIGNWrm64")>; + +def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 6; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup50], (instregex "ADD64rm")>; +def: InstRW<[SBWriteResGroup50], (instregex "ADD8rm")>; +def: InstRW<[SBWriteResGroup50], (instregex "AND64rm")>; +def: InstRW<[SBWriteResGroup50], (instregex "AND8rm")>; +def: InstRW<[SBWriteResGroup50], (instregex "CMP64mi8")>; +def: InstRW<[SBWriteResGroup50], (instregex "CMP64mr")>; +def: InstRW<[SBWriteResGroup50], (instregex "CMP64rm")>; +def: InstRW<[SBWriteResGroup50], (instregex "CMP8mi")>; +def: InstRW<[SBWriteResGroup50], (instregex "CMP8mr")>; +def: InstRW<[SBWriteResGroup50], (instregex "CMP8rm")>; +def: InstRW<[SBWriteResGroup50], (instregex "LODSL")>; +def: InstRW<[SBWriteResGroup50], (instregex "LODSQ")>; +def: InstRW<[SBWriteResGroup50], (instregex "OR64rm")>; +def: InstRW<[SBWriteResGroup50], (instregex "OR8rm")>; +def: InstRW<[SBWriteResGroup50], (instregex "SUB64rm")>; +def: InstRW<[SBWriteResGroup50], (instregex "SUB8rm")>; +def: InstRW<[SBWriteResGroup50], (instregex "XOR64rm")>; +def: InstRW<[SBWriteResGroup50], (instregex "XOR8rm")>; +def: InstRW<[SBWriteResGroup50], (instregex "POP64rmm")>; +def: InstRW<[SBWriteResGroup50], (instregex "PUSH64rmm")>; + +def SBWriteResGroup51 : SchedWriteRes<[SBPort23]> { + let Latency = 7; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup51], (instregex "VBROADCASTSDYrm")>; +def: InstRW<[SBWriteResGroup51], (instregex "VBROADCASTSSrm")>; +def: InstRW<[SBWriteResGroup51], (instregex "VMOVAPDYrm")>; +def: InstRW<[SBWriteResGroup51], (instregex "VMOVAPSYrm")>; +def: InstRW<[SBWriteResGroup51], (instregex "VMOVDDUPYrm")>; +def: InstRW<[SBWriteResGroup51], (instregex "VMOVDQAYrm")>; +def: InstRW<[SBWriteResGroup51], (instregex "VMOVDQUYrm")>; +def: InstRW<[SBWriteResGroup51], (instregex "VMOVSHDUPYrm")>; +def: InstRW<[SBWriteResGroup51], (instregex "VMOVSLDUPYrm")>; +def: InstRW<[SBWriteResGroup51], (instregex "VMOVUPDYrm")>; +def: InstRW<[SBWriteResGroup51], (instregex "VMOVUPSYrm")>; + +def SBWriteResGroup52 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup52], (instregex "CVTPS2PDrm")>; +def: InstRW<[SBWriteResGroup52], (instregex "CVTSS2SDrm")>; +def: InstRW<[SBWriteResGroup52], (instregex "VCVTPS2PDYrm")>; +def: InstRW<[SBWriteResGroup52], (instregex "VCVTPS2PDrm")>; +def: InstRW<[SBWriteResGroup52], (instregex "VCVTSS2SDrm")>; +def: InstRW<[SBWriteResGroup52], (instregex "VTESTPDrm")>; +def: InstRW<[SBWriteResGroup52], (instregex "VTESTPSrm")>; + +def SBWriteResGroup53 : SchedWriteRes<[SBPort5,SBPort23]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup53], (instregex "ANDNPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "ANDNPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "ANDPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "ANDPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "INSERTPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "MOVHPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "MOVHPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "MOVLPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "MOVLPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "ORPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "ORPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "SHUFPDrmi")>; +def: InstRW<[SBWriteResGroup53], (instregex "SHUFPSrmi")>; +def: InstRW<[SBWriteResGroup53], (instregex "UNPCKHPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "UNPCKHPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "UNPCKLPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "UNPCKLPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VANDNPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VANDNPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VANDPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VANDPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VBROADCASTF128")>; +def: InstRW<[SBWriteResGroup53], (instregex "VINSERTPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VMOVHPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VMOVHPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VMOVLPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VMOVLPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VORPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VORPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VPERMILPDmi")>; +def: InstRW<[SBWriteResGroup53], (instregex "VPERMILPDri")>; +def: InstRW<[SBWriteResGroup53], (instregex "VPERMILPSmi")>; +def: InstRW<[SBWriteResGroup53], (instregex "VPERMILPSri")>; +def: InstRW<[SBWriteResGroup53], (instregex "VSHUFPDrmi")>; +def: InstRW<[SBWriteResGroup53], (instregex "VSHUFPSrmi")>; +def: InstRW<[SBWriteResGroup53], (instregex "VUNPCKHPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VUNPCKHPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VUNPCKLPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VUNPCKLPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VXORPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "VXORPSrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "XORPDrm")>; +def: InstRW<[SBWriteResGroup53], (instregex "XORPSrm")>; + +def SBWriteResGroup54 : SchedWriteRes<[SBPort5,SBPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup54], (instregex "AESDECLASTrr")>; +def: InstRW<[SBWriteResGroup54], (instregex "AESDECrr")>; +def: InstRW<[SBWriteResGroup54], (instregex "AESENCLASTrr")>; +def: InstRW<[SBWriteResGroup54], (instregex "AESENCrr")>; +def: InstRW<[SBWriteResGroup54], (instregex "KANDQrr")>; +def: InstRW<[SBWriteResGroup54], (instregex "VAESDECLASTrr")>; +def: InstRW<[SBWriteResGroup54], (instregex "VAESDECrr")>; +def: InstRW<[SBWriteResGroup54], (instregex "VAESENCrr")>; + +def SBWriteResGroup55 : SchedWriteRes<[SBPort23,SBPort0]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup55], (instregex "BLENDPDrmi")>; +def: InstRW<[SBWriteResGroup55], (instregex "BLENDPSrmi")>; +def: InstRW<[SBWriteResGroup55], (instregex "VBLENDPDrmi")>; +def: InstRW<[SBWriteResGroup55], (instregex "VBLENDPSrmi")>; +def: InstRW<[SBWriteResGroup55], (instregex "VINSERTF128rm")>; + +def SBWriteResGroup56 : SchedWriteRes<[SBPort23,SBPort15]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup56], (instregex "MMX_PADDQirm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PABSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PABSDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PABSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PACKSSDWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PACKSSWBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PACKUSDWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PACKUSWBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PADDBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PADDDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PADDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PADDSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PADDSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PADDUSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PADDUSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PADDWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PALIGNRrmi")>; +def: InstRW<[SBWriteResGroup56], (instregex "PAVGBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PAVGWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PBLENDWrmi")>; +def: InstRW<[SBWriteResGroup56], (instregex "PCMPEQBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PCMPEQDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PCMPEQQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PCMPEQWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PCMPGTBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PCMPGTDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PCMPGTWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PINSRBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PINSRDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PINSRQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PINSRWrmi")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMAXSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMAXSDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMAXSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMAXUBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMAXUDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMAXUWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMINSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMINSDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMINSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMINUBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMINUDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMINUWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMOVSXBDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMOVSXBQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMOVSXBWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMOVSXDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMOVSXWDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMOVSXWQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMOVZXBDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMOVZXBQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMOVZXBWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMOVZXDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMOVZXWDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PMOVZXWQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSHUFBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSHUFDmi")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSHUFHWmi")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSHUFLWmi")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSIGNBrm128")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSIGNDrm128")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSIGNWrm128")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSUBBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSUBDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSUBQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSUBSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSUBSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSUBUSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSUBUSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PSUBWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PUNPCKHBWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PUNPCKHDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PUNPCKHQDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PUNPCKHWDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PUNPCKLBWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PUNPCKLDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PUNPCKLQDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "PUNPCKLWDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPABSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPABSDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPABSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPACKSSDWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPACKSSWBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPACKUSDWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPACKUSWBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPADDBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPADDDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPADDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPADDSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPADDSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPADDUSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPADDUSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPADDWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPALIGNRrmi")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPAVGBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPAVGWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPBLENDWrmi")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPCMPEQBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPCMPEQDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPCMPEQQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPCMPEQWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPCMPGTBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPCMPGTDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPCMPGTWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPINSRBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPINSRDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPINSRQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPINSRWrmi")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMAXSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMAXSDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMAXSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMAXUBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMAXUDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMAXUWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMINSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMINSDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMINSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMINUBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMINUDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMINUWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMOVSXBDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMOVSXBQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMOVSXBWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMOVSXDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMOVSXWDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMOVSXWQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMOVZXBDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMOVZXBQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMOVZXBWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMOVZXDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMOVZXWDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPMOVZXWQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSHUFBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSHUFDmi")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSHUFHWmi")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSHUFLWmi")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSIGNBrm128")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSIGNDrm128")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSIGNWrm128")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSUBBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSUBDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSUBQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSUBSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSUBSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSUBUSBrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSUBUSWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPSUBWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPUNPCKHBWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPUNPCKHDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPUNPCKHQDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPUNPCKHWDrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPUNPCKLBWrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPUNPCKLDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPUNPCKLQDQrm")>; +def: InstRW<[SBWriteResGroup56], (instregex "VPUNPCKLWDrm")>; + +def SBWriteResGroup57 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 7; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup57], (instregex "PANDNrm")>; +def: InstRW<[SBWriteResGroup57], (instregex "PANDrm")>; +def: InstRW<[SBWriteResGroup57], (instregex "PORrm")>; +def: InstRW<[SBWriteResGroup57], (instregex "PXORrm")>; +def: InstRW<[SBWriteResGroup57], (instregex "VPANDNrm")>; +def: InstRW<[SBWriteResGroup57], (instregex "VPANDrm")>; +def: InstRW<[SBWriteResGroup57], (instregex "VPORrm")>; +def: InstRW<[SBWriteResGroup57], (instregex "VPXORrm")>; + +def SBWriteResGroup58 : SchedWriteRes<[SBPort0,SBPort0]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SBWriteResGroup58], (instregex "VRCPPSr")>; +def: InstRW<[SBWriteResGroup58], (instregex "VRSQRTPSYr")>; + +def SBWriteResGroup59 : SchedWriteRes<[SBPort5,SBPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SBWriteResGroup59], (instregex "VERRm")>; +def: InstRW<[SBWriteResGroup59], (instregex "VERWm")>; + +def SBWriteResGroup60 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup60], (instregex "LODSB")>; +def: InstRW<[SBWriteResGroup60], (instregex "LODSW")>; + +def SBWriteResGroup61 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup61], (instregex "FARJMP64")>; + +def SBWriteResGroup62 : SchedWriteRes<[SBPort23,SBPort0,SBPort015]> { + let Latency = 7; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup62], (instregex "ADC64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "ADC8rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVAE64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVB64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVE64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVG64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVGE64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVL64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVLE64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVNE64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVNO64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVNP64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVNS64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVO64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVP64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "CMOVS64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "SBB64rm")>; +def: InstRW<[SBWriteResGroup62], (instregex "SBB8rm")>; + +def SBWriteResGroup63 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup63], (instregex "FNSTSWm")>; + +def SBWriteResGroup64 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SBWriteResGroup64], (instregex "SLDT32r")>; +def: InstRW<[SBWriteResGroup64], (instregex "STR32r")>; + +def SBWriteResGroup65 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup65], (instregex "CALL64m")>; +def: InstRW<[SBWriteResGroup65], (instregex "FNSTCW16m")>; + +def SBWriteResGroup66 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SBWriteResGroup66], (instregex "BTC64mi8")>; +def: InstRW<[SBWriteResGroup66], (instregex "BTR64mi8")>; +def: InstRW<[SBWriteResGroup66], (instregex "BTS64mi8")>; +def: InstRW<[SBWriteResGroup66], (instregex "SAR64mi")>; +def: InstRW<[SBWriteResGroup66], (instregex "SAR8mi")>; +def: InstRW<[SBWriteResGroup66], (instregex "SHL64m1")>; +def: InstRW<[SBWriteResGroup66], (instregex "SHL64mi")>; +def: InstRW<[SBWriteResGroup66], (instregex "SHL8m1")>; +def: InstRW<[SBWriteResGroup66], (instregex "SHL8mi")>; +def: InstRW<[SBWriteResGroup66], (instregex "SHR64mi")>; +def: InstRW<[SBWriteResGroup66], (instregex "SHR8mi")>; + +def SBWriteResGroup67 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { + let Latency = 7; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SBWriteResGroup67], (instregex "ADD64mi8")>; +def: InstRW<[SBWriteResGroup67], (instregex "ADD64mr")>; +def: InstRW<[SBWriteResGroup67], (instregex "ADD8mi")>; +def: InstRW<[SBWriteResGroup67], (instregex "ADD8mr")>; +def: InstRW<[SBWriteResGroup67], (instregex "AND64mi8")>; +def: InstRW<[SBWriteResGroup67], (instregex "AND64mr")>; +def: InstRW<[SBWriteResGroup67], (instregex "AND8mi")>; +def: InstRW<[SBWriteResGroup67], (instregex "AND8mr")>; +def: InstRW<[SBWriteResGroup67], (instregex "DEC64m")>; +def: InstRW<[SBWriteResGroup67], (instregex "DEC8m")>; +def: InstRW<[SBWriteResGroup67], (instregex "INC64m")>; +def: InstRW<[SBWriteResGroup67], (instregex "INC8m")>; +def: InstRW<[SBWriteResGroup67], (instregex "NEG64m")>; +def: InstRW<[SBWriteResGroup67], (instregex "NEG8m")>; +def: InstRW<[SBWriteResGroup67], (instregex "NOT64m")>; +def: InstRW<[SBWriteResGroup67], (instregex "NOT8m")>; +def: InstRW<[SBWriteResGroup67], (instregex "OR64mi8")>; +def: InstRW<[SBWriteResGroup67], (instregex "OR64mr")>; +def: InstRW<[SBWriteResGroup67], (instregex "OR8mi")>; +def: InstRW<[SBWriteResGroup67], (instregex "OR8mr")>; +def: InstRW<[SBWriteResGroup67], (instregex "SUB64mi8")>; +def: InstRW<[SBWriteResGroup67], (instregex "SUB64mr")>; +def: InstRW<[SBWriteResGroup67], (instregex "SUB8mi")>; +def: InstRW<[SBWriteResGroup67], (instregex "SUB8mr")>; +def: InstRW<[SBWriteResGroup67], (instregex "TEST64rm")>; +def: InstRW<[SBWriteResGroup67], (instregex "TEST8mi")>; +def: InstRW<[SBWriteResGroup67], (instregex "TEST8rm")>; +def: InstRW<[SBWriteResGroup67], (instregex "XOR64mi8")>; +def: InstRW<[SBWriteResGroup67], (instregex "XOR64mr")>; +def: InstRW<[SBWriteResGroup67], (instregex "XOR8mi")>; +def: InstRW<[SBWriteResGroup67], (instregex "XOR8mr")>; + +def SBWriteResGroup68 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup68], (instregex "MMX_PMADDUBSWrm64")>; +def: InstRW<[SBWriteResGroup68], (instregex "MMX_PMULHRSWrm64")>; +def: InstRW<[SBWriteResGroup68], (instregex "VTESTPDYrm")>; +def: InstRW<[SBWriteResGroup68], (instregex "VTESTPSYrm")>; + +def SBWriteResGroup69 : SchedWriteRes<[SBPort1,SBPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup69], (instregex "BSF64rm")>; +def: InstRW<[SBWriteResGroup69], (instregex "BSR64rm")>; +def: InstRW<[SBWriteResGroup69], (instregex "CRC32r32m16")>; +def: InstRW<[SBWriteResGroup69], (instregex "CRC32r32m8")>; +def: InstRW<[SBWriteResGroup69], (instregex "MUL8m")>; + +def SBWriteResGroup70 : SchedWriteRes<[SBPort5,SBPort23]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup70], (instregex "VANDNPDYrm")>; +def: InstRW<[SBWriteResGroup70], (instregex "VANDNPSYrm")>; +def: InstRW<[SBWriteResGroup70], (instregex "VANDPDrm")>; +def: InstRW<[SBWriteResGroup70], (instregex "VANDPSrm")>; +def: InstRW<[SBWriteResGroup70], (instregex "VORPDYrm")>; +def: InstRW<[SBWriteResGroup70], (instregex "VORPSYrm")>; +def: InstRW<[SBWriteResGroup70], (instregex "VPERM2F128rm")>; +def: InstRW<[SBWriteResGroup70], (instregex "VPERMILPDYri")>; +def: InstRW<[SBWriteResGroup70], (instregex "VPERMILPDmi")>; +def: InstRW<[SBWriteResGroup70], (instregex "VPERMILPSYri")>; +def: InstRW<[SBWriteResGroup70], (instregex "VPERMILPSmi")>; +def: InstRW<[SBWriteResGroup70], (instregex "VSHUFPDYrmi")>; +def: InstRW<[SBWriteResGroup70], (instregex "VSHUFPSYrmi")>; +def: InstRW<[SBWriteResGroup70], (instregex "VUNPCKHPDrm")>; +def: InstRW<[SBWriteResGroup70], (instregex "VUNPCKHPSrm")>; +def: InstRW<[SBWriteResGroup70], (instregex "VUNPCKLPDYrm")>; +def: InstRW<[SBWriteResGroup70], (instregex "VUNPCKLPSYrm")>; +def: InstRW<[SBWriteResGroup70], (instregex "VXORPDrm")>; +def: InstRW<[SBWriteResGroup70], (instregex "VXORPSrm")>; + +def SBWriteResGroup71 : SchedWriteRes<[SBPort23,SBPort0]> { + let Latency = 8; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup71], (instregex "VBLENDPDYrmi")>; +def: InstRW<[SBWriteResGroup71], (instregex "VBLENDPSYrmi")>; + +def SBWriteResGroup72 : SchedWriteRes<[SBPort23,SBPort0]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup72], (instregex "BLENDVPDrm0")>; +def: InstRW<[SBWriteResGroup72], (instregex "BLENDVPSrm0")>; +def: InstRW<[SBWriteResGroup72], (instregex "VBLENDVPDrm")>; +def: InstRW<[SBWriteResGroup72], (instregex "VBLENDVPSrm")>; +def: InstRW<[SBWriteResGroup72], (instregex "VMASKMOVPDrm")>; +def: InstRW<[SBWriteResGroup72], (instregex "VMASKMOVPSrm")>; + +def SBWriteResGroup73 : SchedWriteRes<[SBPort23,SBPort15]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup73], (instregex "PBLENDVBrr0")>; +def: InstRW<[SBWriteResGroup73], (instregex "VPBLENDVBrm")>; + +def SBWriteResGroup74 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup74], (instregex "COMISDrm")>; +def: InstRW<[SBWriteResGroup74], (instregex "COMISSrm")>; +def: InstRW<[SBWriteResGroup74], (instregex "UCOMISDrm")>; +def: InstRW<[SBWriteResGroup74], (instregex "UCOMISSrm")>; +def: InstRW<[SBWriteResGroup74], (instregex "VCOMISDrm")>; +def: InstRW<[SBWriteResGroup74], (instregex "VCOMISSrm")>; +def: InstRW<[SBWriteResGroup74], (instregex "VUCOMISDrm")>; +def: InstRW<[SBWriteResGroup74], (instregex "VUCOMISSrm")>; + +def SBWriteResGroup75 : SchedWriteRes<[SBPort0,SBPort5,SBPort23]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup75], (instregex "PTESTrm")>; +def: InstRW<[SBWriteResGroup75], (instregex "VPTESTrm")>; + +def SBWriteResGroup76 : SchedWriteRes<[SBPort0,SBPort23,SBPort15]> { + let Latency = 8; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup76], (instregex "PSLLDrm")>; +def: InstRW<[SBWriteResGroup76], (instregex "PSLLQrm")>; +def: InstRW<[SBWriteResGroup76], (instregex "PSLLWrm")>; +def: InstRW<[SBWriteResGroup76], (instregex "PSRADrm")>; +def: InstRW<[SBWriteResGroup76], (instregex "PSRAWrm")>; +def: InstRW<[SBWriteResGroup76], (instregex "PSRLDrm")>; +def: InstRW<[SBWriteResGroup76], (instregex "PSRLQrm")>; +def: InstRW<[SBWriteResGroup76], (instregex "PSRLWrm")>; +def: InstRW<[SBWriteResGroup76], (instregex "VPSLLDri")>; +def: InstRW<[SBWriteResGroup76], (instregex "VPSLLQri")>; +def: InstRW<[SBWriteResGroup76], (instregex "VPSLLWri")>; +def: InstRW<[SBWriteResGroup76], (instregex "VPSRADrm")>; +def: InstRW<[SBWriteResGroup76], (instregex "VPSRAWrm")>; +def: InstRW<[SBWriteResGroup76], (instregex "VPSRLDrm")>; +def: InstRW<[SBWriteResGroup76], (instregex "VPSRLQrm")>; +def: InstRW<[SBWriteResGroup76], (instregex "VPSRLWrm")>; + +def SBWriteResGroup77 : SchedWriteRes<[SBPort23,SBPort15]> { + let Latency = 8; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SBWriteResGroup77], (instregex "MMX_PHADDSWrm64")>; +def: InstRW<[SBWriteResGroup77], (instregex "MMX_PHADDWrm64")>; +def: InstRW<[SBWriteResGroup77], (instregex "MMX_PHADDrm64")>; +def: InstRW<[SBWriteResGroup77], (instregex "MMX_PHSUBDrm64")>; +def: InstRW<[SBWriteResGroup77], (instregex "MMX_PHSUBSWrm64")>; +def: InstRW<[SBWriteResGroup77], (instregex "MMX_PHSUBWrm64")>; + +def SBWriteResGroup78 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 8; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SBWriteResGroup78], (instregex "CMPXCHG64rm")>; +def: InstRW<[SBWriteResGroup78], (instregex "CMPXCHG8rm")>; + +def SBWriteResGroup79 : SchedWriteRes<[SBPort23,SBPort0,SBPort015]> { + let Latency = 8; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SBWriteResGroup79], (instregex "CMOVA64rm")>; +def: InstRW<[SBWriteResGroup79], (instregex "CMOVBE64rm")>; + +def SBWriteResGroup80 : SchedWriteRes<[SBPort23,SBPort015]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [2,3]; +} +def: InstRW<[SBWriteResGroup80], (instregex "CMPSB")>; +def: InstRW<[SBWriteResGroup80], (instregex "CMPSL")>; +def: InstRW<[SBWriteResGroup80], (instregex "CMPSQ")>; +def: InstRW<[SBWriteResGroup80], (instregex "CMPSW")>; + +def SBWriteResGroup81 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,2,2]; +} +def: InstRW<[SBWriteResGroup81], (instregex "FLDCW16m")>; + +def SBWriteResGroup82 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,2,2]; +} +def: InstRW<[SBWriteResGroup82], (instregex "ROL64mi")>; +def: InstRW<[SBWriteResGroup82], (instregex "ROL8mi")>; +def: InstRW<[SBWriteResGroup82], (instregex "ROR64mi")>; +def: InstRW<[SBWriteResGroup82], (instregex "ROR8mi")>; + +def SBWriteResGroup83 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,2,2]; +} +def: InstRW<[SBWriteResGroup83], (instregex "MOVSB")>; +def: InstRW<[SBWriteResGroup83], (instregex "MOVSL")>; +def: InstRW<[SBWriteResGroup83], (instregex "MOVSQ")>; +def: InstRW<[SBWriteResGroup83], (instregex "MOVSW")>; +def: InstRW<[SBWriteResGroup83], (instregex "XADD64rm")>; +def: InstRW<[SBWriteResGroup83], (instregex "XADD8rm")>; + +def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,1,1,2]; +} +def: InstRW<[SBWriteResGroup84], (instregex "FARCALL64")>; + +def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> { + let Latency = 8; + let NumMicroOps = 5; + let ResourceCycles = [1,2,1,1]; +} +def: InstRW<[SBWriteResGroup85], (instregex "SHLD64mri8")>; +def: InstRW<[SBWriteResGroup85], (instregex "SHRD64mri8")>; + +def SBWriteResGroup86 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup86], (instregex "MMX_PMULUDQirm")>; +def: InstRW<[SBWriteResGroup86], (instregex "PMADDUBSWrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "PMADDWDrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "PMULDQrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "PMULHRSWrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "PMULHUWrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "PMULHWrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "PMULLDrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "PMULLWrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "PMULUDQrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "PSADBWrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "VPMADDUBSWrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "VPMADDWDrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "VPMULDQrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "VPMULHRSWrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "VPMULHUWrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "VPMULHWrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "VPMULLDrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "VPMULLWrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "VPMULUDQrm")>; +def: InstRW<[SBWriteResGroup86], (instregex "VPSADBWrm")>; + +def SBWriteResGroup87 : SchedWriteRes<[SBPort1,SBPort23]> { + let Latency = 9; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup87], (instregex "ADDPDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "ADDPSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "ADDSDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "ADDSSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "ADDSUBPDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "ADDSUBPSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "CMPPDrmi")>; +def: InstRW<[SBWriteResGroup87], (instregex "CMPPSrmi")>; +def: InstRW<[SBWriteResGroup87], (instregex "CMPSSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "CVTDQ2PSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "CVTPS2DQrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "CVTSI2SD64rm")>; +def: InstRW<[SBWriteResGroup87], (instregex "CVTSI2SDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "CVTTPS2DQrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "MAXPDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "MAXPSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "MAXSDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "MAXSSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "MINPDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "MINPSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "MINSDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "MINSSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "MMX_CVTPI2PSirm")>; +def: InstRW<[SBWriteResGroup87], (instregex "MMX_CVTPS2PIirm")>; +def: InstRW<[SBWriteResGroup87], (instregex "MMX_CVTTPS2PIirm")>; +def: InstRW<[SBWriteResGroup87], (instregex "POPCNT64rm")>; +def: InstRW<[SBWriteResGroup87], (instregex "ROUNDPDm")>; +def: InstRW<[SBWriteResGroup87], (instregex "ROUNDPSm")>; +def: InstRW<[SBWriteResGroup87], (instregex "ROUNDSDm")>; +def: InstRW<[SBWriteResGroup87], (instregex "ROUNDSSm")>; +def: InstRW<[SBWriteResGroup87], (instregex "SUBPDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "SUBPSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "SUBSDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "SUBSSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VADDPDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VADDPSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VADDSDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VADDSSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VADDSUBPDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VADDSUBPSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VCMPPDrmi")>; +def: InstRW<[SBWriteResGroup87], (instregex "VCMPPSrmi")>; +def: InstRW<[SBWriteResGroup87], (instregex "VCMPSDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VCMPSSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VCVTDQ2PSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VCVTPS2DQrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VCVTSI2SD64rm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VCVTSI2SDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VCVTTPS2DQrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VMAXPDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VMAXPSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VMAXSDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VMAXSSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VMINPDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VMINPSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VMINSDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VMINSSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VROUNDPDm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VROUNDPSm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VROUNDSDm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VROUNDSSm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VSUBPDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VSUBPSrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VSUBSDrm")>; +def: InstRW<[SBWriteResGroup87], (instregex "VSUBSSrm")>; + +def SBWriteResGroup88 : SchedWriteRes<[SBPort23,SBPort0]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,2]; +} +def: InstRW<[SBWriteResGroup88], (instregex "VBLENDVPDYrm")>; +def: InstRW<[SBWriteResGroup88], (instregex "VBLENDVPSYrm")>; +def: InstRW<[SBWriteResGroup88], (instregex "VMASKMOVPDrm")>; +def: InstRW<[SBWriteResGroup88], (instregex "VMASKMOVPSrm")>; + +def SBWriteResGroup89 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup89], (instregex "DPPDrri")>; +def: InstRW<[SBWriteResGroup89], (instregex "VDPPDrri")>; + +def SBWriteResGroup90 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup90], (instregex "CVTSD2SI64rm")>; +def: InstRW<[SBWriteResGroup90], (instregex "CVTSD2SIrm")>; +def: InstRW<[SBWriteResGroup90], (instregex "CVTSS2SI64rm")>; +def: InstRW<[SBWriteResGroup90], (instregex "CVTSS2SIrm")>; +def: InstRW<[SBWriteResGroup90], (instregex "CVTTSD2SI64rm")>; +def: InstRW<[SBWriteResGroup90], (instregex "CVTTSD2SIrm")>; +def: InstRW<[SBWriteResGroup90], (instregex "CVTTSS2SI64rm")>; +def: InstRW<[SBWriteResGroup90], (instregex "CVTTSS2SIrm")>; +def: InstRW<[SBWriteResGroup90], (instregex "MUL64m")>; + +def SBWriteResGroup91 : SchedWriteRes<[SBPort0,SBPort5,SBPort23]> { + let Latency = 9; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup91], (instregex "VPTESTYrm")>; + +def SBWriteResGroup92 : SchedWriteRes<[SBPort23,SBPort15]> { + let Latency = 9; + let NumMicroOps = 4; + let ResourceCycles = [1,3]; +} +def: InstRW<[SBWriteResGroup92], (instregex "PHADDDrm")>; +def: InstRW<[SBWriteResGroup92], (instregex "PHADDSWrm128")>; +def: InstRW<[SBWriteResGroup92], (instregex "PHADDWrm")>; +def: InstRW<[SBWriteResGroup92], (instregex "PHSUBDrm")>; +def: InstRW<[SBWriteResGroup92], (instregex "PHSUBSWrm128")>; +def: InstRW<[SBWriteResGroup92], (instregex "PHSUBWrm")>; +def: InstRW<[SBWriteResGroup92], (instregex "VPHADDDrm")>; +def: InstRW<[SBWriteResGroup92], (instregex "VPHADDSWrm128")>; +def: InstRW<[SBWriteResGroup92], (instregex "VPHADDWrm")>; +def: InstRW<[SBWriteResGroup92], (instregex "VPHSUBDrm")>; +def: InstRW<[SBWriteResGroup92], (instregex "VPHSUBSWrm128")>; +def: InstRW<[SBWriteResGroup92], (instregex "VPHSUBWrm")>; +def: InstRW<[SBWriteResGroup92], (instregex "SHL64mCL")>; +def: InstRW<[SBWriteResGroup92], (instregex "SHL8mCL")>; + +def SBWriteResGroup93 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,2,3]; +} +def: InstRW<[SBWriteResGroup93], (instregex "ADC64mi8")>; +def: InstRW<[SBWriteResGroup93], (instregex "ADC8mi")>; +def: InstRW<[SBWriteResGroup93], (instregex "SBB64mi8")>; +def: InstRW<[SBWriteResGroup93], (instregex "SBB8mi")>; + +def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,2,2,1]; +} +def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>; +def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>; +def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>; +def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>; + +def SBWriteResGroup95 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort0,SBPort015]> { + let Latency = 9; + let NumMicroOps = 6; + let ResourceCycles = [1,1,2,1,1]; +} +def: InstRW<[SBWriteResGroup95], (instregex "BT64mr")>; +def: InstRW<[SBWriteResGroup95], (instregex "BTC64mr")>; +def: InstRW<[SBWriteResGroup95], (instregex "BTR64mr")>; +def: InstRW<[SBWriteResGroup95], (instregex "BTS64mr")>; +def: InstRW<[SBWriteResGroup95], (instregex "VADDPDYrm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VADDPSYrm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VADDSUBPDYrm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VADDSUBPSYrm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VCMPPDYrmi")>; +def: InstRW<[SBWriteResGroup95], (instregex "VCMPPSYrmi")>; +def: InstRW<[SBWriteResGroup95], (instregex "VCVTDQ2PSYrm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VCVTPS2DQYrm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VCVTTPS2DQrm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VMAXPDYrm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VMAXPSYrm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VMINPDrm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VMINPSrm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VROUNDPDm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VROUNDPSm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VSUBPDYrm")>; +def: InstRW<[SBWriteResGroup95], (instregex "VSUBPSYrm")>; + +def SBWriteResGroup96 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup96], (instregex "VCVTSD2SI64rm")>; +def: InstRW<[SBWriteResGroup96], (instregex "VCVTSD2SI64rr")>; +def: InstRW<[SBWriteResGroup96], (instregex "VCVTSS2SI64rm")>; +def: InstRW<[SBWriteResGroup96], (instregex "VCVTSS2SIrm")>; +def: InstRW<[SBWriteResGroup96], (instregex "VCVTTSD2SI64rm")>; +def: InstRW<[SBWriteResGroup96], (instregex "VCVTTSD2SI64rr")>; +def: InstRW<[SBWriteResGroup96], (instregex "VCVTTSS2SI64rm")>; +def: InstRW<[SBWriteResGroup96], (instregex "VCVTTSS2SIrm")>; + +def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> { + let Latency = 10; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup97], (instregex "CVTDQ2PDrm")>; +def: InstRW<[SBWriteResGroup97], (instregex "CVTPD2DQrm")>; +def: InstRW<[SBWriteResGroup97], (instregex "CVTPD2PSrm")>; +def: InstRW<[SBWriteResGroup97], (instregex "CVTSD2SSrm")>; +def: InstRW<[SBWriteResGroup97], (instregex "CVTSI2SS64rm")>; +def: InstRW<[SBWriteResGroup97], (instregex "CVTSI2SSrm")>; +def: InstRW<[SBWriteResGroup97], (instregex "CVTTPD2DQrm")>; +def: InstRW<[SBWriteResGroup97], (instregex "MMX_CVTPD2PIirm")>; +def: InstRW<[SBWriteResGroup97], (instregex "MMX_CVTPI2PDirm")>; +def: InstRW<[SBWriteResGroup97], (instregex "MMX_CVTTPD2PIirm")>; +def: InstRW<[SBWriteResGroup97], (instregex "VCVTDQ2PDYrm")>; +def: InstRW<[SBWriteResGroup97], (instregex "VCVTDQ2PDrm")>; +def: InstRW<[SBWriteResGroup97], (instregex "VCVTPD2DQrm")>; +def: InstRW<[SBWriteResGroup97], (instregex "VCVTPD2PSrm")>; +def: InstRW<[SBWriteResGroup97], (instregex "VCVTSD2SSrm")>; +def: InstRW<[SBWriteResGroup97], (instregex "VCVTSI2SS64rm")>; +def: InstRW<[SBWriteResGroup97], (instregex "VCVTSI2SSrm")>; +def: InstRW<[SBWriteResGroup97], (instregex "VCVTTPD2DQrm")>; + +def SBWriteResGroup98 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 11; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup98], (instregex "MULPDrm")>; +def: InstRW<[SBWriteResGroup98], (instregex "MULPSrm")>; +def: InstRW<[SBWriteResGroup98], (instregex "MULSDrm")>; +def: InstRW<[SBWriteResGroup98], (instregex "MULSSrm")>; +def: InstRW<[SBWriteResGroup98], (instregex "PCMPGTQrm")>; +def: InstRW<[SBWriteResGroup98], (instregex "PHMINPOSUWrm128")>; +def: InstRW<[SBWriteResGroup98], (instregex "RCPPSm")>; +def: InstRW<[SBWriteResGroup98], (instregex "RCPSSm")>; +def: InstRW<[SBWriteResGroup98], (instregex "RSQRTPSm")>; +def: InstRW<[SBWriteResGroup98], (instregex "RSQRTSSm")>; +def: InstRW<[SBWriteResGroup98], (instregex "VMULPDrm")>; +def: InstRW<[SBWriteResGroup98], (instregex "VMULPSrm")>; +def: InstRW<[SBWriteResGroup98], (instregex "VMULSDrm")>; +def: InstRW<[SBWriteResGroup98], (instregex "VMULSSrm")>; +def: InstRW<[SBWriteResGroup98], (instregex "VPCMPGTQrm")>; +def: InstRW<[SBWriteResGroup98], (instregex "VPHMINPOSUWrm128")>; +def: InstRW<[SBWriteResGroup98], (instregex "VRCPPSm")>; +def: InstRW<[SBWriteResGroup98], (instregex "VRCPSSm")>; +def: InstRW<[SBWriteResGroup98], (instregex "VRSQRTPSm")>; +def: InstRW<[SBWriteResGroup98], (instregex "VRSQRTSSm")>; + +def SBWriteResGroup99 : SchedWriteRes<[SBPort0]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [3]; +} +def: InstRW<[SBWriteResGroup99], (instregex "PCMPISTRIrr")>; +def: InstRW<[SBWriteResGroup99], (instregex "PCMPISTRM128rr")>; +def: InstRW<[SBWriteResGroup99], (instregex "VPCMPISTRIrr")>; +def: InstRW<[SBWriteResGroup99], (instregex "VPCMPISTRM128rr")>; + +def SBWriteResGroup100 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> { + let Latency = 11; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup100], (instregex "VCVTPD2DQYrm")>; +def: InstRW<[SBWriteResGroup100], (instregex "VCVTPD2PSYrm")>; +def: InstRW<[SBWriteResGroup100], (instregex "VCVTTPD2DQYrm")>; + +def SBWriteResGroup101 : SchedWriteRes<[SBPort0,SBPort23,SBPort15]> { + let Latency = 11; + let NumMicroOps = 4; + let ResourceCycles = [1,1,2]; +} +def: InstRW<[SBWriteResGroup101], (instregex "MPSADBWrmi")>; +def: InstRW<[SBWriteResGroup101], (instregex "VMPSADBWrmi")>; + +def SBWriteResGroup102 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> { + let Latency = 11; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SBWriteResGroup102], (instregex "HADDPDrm")>; +def: InstRW<[SBWriteResGroup102], (instregex "HADDPSrm")>; +def: InstRW<[SBWriteResGroup102], (instregex "HSUBPDrm")>; +def: InstRW<[SBWriteResGroup102], (instregex "HSUBPSrm")>; +def: InstRW<[SBWriteResGroup102], (instregex "VHADDPDrm")>; +def: InstRW<[SBWriteResGroup102], (instregex "VHADDPSrm")>; +def: InstRW<[SBWriteResGroup102], (instregex "VHSUBPDrm")>; +def: InstRW<[SBWriteResGroup102], (instregex "VHSUBPSrm")>; + +def SBWriteResGroup103 : SchedWriteRes<[SBPort5]> { + let Latency = 12; + let NumMicroOps = 2; + let ResourceCycles = [2]; +} +def: InstRW<[SBWriteResGroup103], (instregex "AESIMCrr")>; +def: InstRW<[SBWriteResGroup103], (instregex "VAESIMCrr")>; +def: InstRW<[SBWriteResGroup103], (instregex "VMULPDYrm")>; +def: InstRW<[SBWriteResGroup103], (instregex "VMULPSYrm")>; + +def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> { + let Latency = 12; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SBWriteResGroup104], (instregex "DPPSrri")>; +def: InstRW<[SBWriteResGroup104], (instregex "VDPPSYrri")>; +def: InstRW<[SBWriteResGroup104], (instregex "VDPPSrri")>; + +def SBWriteResGroup105 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> { + let Latency = 12; + let NumMicroOps = 4; + let ResourceCycles = [1,2,1]; +} +def: InstRW<[SBWriteResGroup105], (instregex "VHADDPDrm")>; +def: InstRW<[SBWriteResGroup105], (instregex "VHADDPSYrm")>; +def: InstRW<[SBWriteResGroup105], (instregex "VHSUBPDYrm")>; +def: InstRW<[SBWriteResGroup105], (instregex "VHSUBPSYrm")>; + +def SBWriteResGroup106 : SchedWriteRes<[SBPort5,SBPort23,SBPort015]> { + let Latency = 13; + let NumMicroOps = 3; + let ResourceCycles = [1,1,1]; +} +def: InstRW<[SBWriteResGroup106], (instregex "AESDECLASTrm")>; +def: InstRW<[SBWriteResGroup106], (instregex "AESDECrm")>; +def: InstRW<[SBWriteResGroup106], (instregex "AESENCLASTrm")>; +def: InstRW<[SBWriteResGroup106], (instregex "AESENCrm")>; +def: InstRW<[SBWriteResGroup106], (instregex "VAESDECLASTrm")>; +def: InstRW<[SBWriteResGroup106], (instregex "VAESDECrm")>; +def: InstRW<[SBWriteResGroup106], (instregex "VAESENCLASTrm")>; +def: InstRW<[SBWriteResGroup106], (instregex "VAESENCrm")>; + +def SBWriteResGroup107 : SchedWriteRes<[SBPort0]> { + let Latency = 14; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup107], (instregex "DIVPSrr")>; +def: InstRW<[SBWriteResGroup107], (instregex "DIVSSrr")>; +def: InstRW<[SBWriteResGroup107], (instregex "SQRTPSr")>; +def: InstRW<[SBWriteResGroup107], (instregex "SQRTSSr")>; +def: InstRW<[SBWriteResGroup107], (instregex "VDIVPSrr")>; +def: InstRW<[SBWriteResGroup107], (instregex "VDIVSSrr")>; +def: InstRW<[SBWriteResGroup107], (instregex "VSQRTPSr")>; + +def SBWriteResGroup108 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 14; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup108], (instregex "VSQRTSSm")>; + +def SBWriteResGroup109 : SchedWriteRes<[SBPort0,SBPort23,SBPort0]> { + let Latency = 14; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SBWriteResGroup109], (instregex "VRCPPSm")>; +def: InstRW<[SBWriteResGroup109], (instregex "VRSQRTPSYm")>; + +def SBWriteResGroup110 : SchedWriteRes<[SBPort0,SBPort1,SBPort5,SBPort23]> { + let Latency = 15; + let NumMicroOps = 4; + let ResourceCycles = [1,1,1,1]; +} +def: InstRW<[SBWriteResGroup110], (instregex "DPPDrmi")>; +def: InstRW<[SBWriteResGroup110], (instregex "VDPPDrmi")>; + +def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 17; + let NumMicroOps = 4; + let ResourceCycles = [3,1]; +} +def: InstRW<[SBWriteResGroup111], (instregex "PCMPISTRIrm")>; +def: InstRW<[SBWriteResGroup111], (instregex "PCMPISTRM128rm")>; +def: InstRW<[SBWriteResGroup111], (instregex "VPCMPISTRIrm")>; +def: InstRW<[SBWriteResGroup111], (instregex "VPCMPISTRM128rm")>; + +def SBWriteResGroup112 : SchedWriteRes<[SBPort5,SBPort23]> { + let Latency = 18; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SBWriteResGroup112], (instregex "AESIMCrm")>; +def: InstRW<[SBWriteResGroup112], (instregex "VAESIMCrm")>; + +def SBWriteResGroup113 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 20; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup113], (instregex "DIVPSrm")>; +def: InstRW<[SBWriteResGroup113], (instregex "DIVSSrm")>; +def: InstRW<[SBWriteResGroup113], (instregex "SQRTPSm")>; +def: InstRW<[SBWriteResGroup113], (instregex "SQRTSSm")>; +def: InstRW<[SBWriteResGroup113], (instregex "VDIVPSrm")>; +def: InstRW<[SBWriteResGroup113], (instregex "VDIVSSrm")>; +def: InstRW<[SBWriteResGroup113], (instregex "VSQRTPSm")>; + +def SBWriteResGroup114 : SchedWriteRes<[SBPort0]> { + let Latency = 21; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup114], (instregex "VSQRTSDr")>; + +def SBWriteResGroup115 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 21; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup115], (instregex "VSQRTSDm")>; + +def SBWriteResGroup116 : SchedWriteRes<[SBPort0]> { + let Latency = 22; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup116], (instregex "DIVPDrr")>; +def: InstRW<[SBWriteResGroup116], (instregex "DIVSDrr")>; +def: InstRW<[SBWriteResGroup116], (instregex "SQRTPDr")>; +def: InstRW<[SBWriteResGroup116], (instregex "SQRTSDr")>; +def: InstRW<[SBWriteResGroup116], (instregex "VDIVPDrr")>; +def: InstRW<[SBWriteResGroup116], (instregex "VDIVSDrr")>; +def: InstRW<[SBWriteResGroup116], (instregex "VSQRTPDr")>; + +def SBWriteResGroup117 : SchedWriteRes<[SBPort0,SBPort23]> { + let Latency = 28; + let NumMicroOps = 2; + let ResourceCycles = [1,1]; +} +def: InstRW<[SBWriteResGroup117], (instregex "DIVPDrm")>; +def: InstRW<[SBWriteResGroup117], (instregex "DIVSDrm")>; +def: InstRW<[SBWriteResGroup117], (instregex "SQRTPDm")>; +def: InstRW<[SBWriteResGroup117], (instregex "SQRTSDm")>; +def: InstRW<[SBWriteResGroup117], (instregex "VDIVPDrm")>; +def: InstRW<[SBWriteResGroup117], (instregex "VDIVSDrm")>; +def: InstRW<[SBWriteResGroup117], (instregex "VSQRTPDm")>; + +def SBWriteResGroup118 : SchedWriteRes<[SBPort0,SBPort0]> { + let Latency = 29; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SBWriteResGroup118], (instregex "VDIVPSYrr")>; +def: InstRW<[SBWriteResGroup118], (instregex "VSQRTPSYr")>; + +def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort23,SBPort0]> { + let Latency = 36; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SBWriteResGroup119], (instregex "VDIVPSYrm")>; +def: InstRW<[SBWriteResGroup119], (instregex "VSQRTPSYm")>; + +def SBWriteResGroup120 : SchedWriteRes<[SBPort0,SBPort0]> { + let Latency = 45; + let NumMicroOps = 3; + let ResourceCycles = [2,1]; +} +def: InstRW<[SBWriteResGroup120], (instregex "VDIVPDYrr")>; +def: InstRW<[SBWriteResGroup120], (instregex "VSQRTPDYr")>; + +def SBWriteResGroup121 : SchedWriteRes<[SBPort0,SBPort23,SBPort0]> { + let Latency = 52; + let NumMicroOps = 4; + let ResourceCycles = [2,1,1]; +} +def: InstRW<[SBWriteResGroup121], (instregex "VDIVPDYrm")>; +def: InstRW<[SBWriteResGroup121], (instregex "VSQRTPDYm")>; + +def SBWriteResGroup122 : SchedWriteRes<[SBPort0]> { + let Latency = 114; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} +def: InstRW<[SBWriteResGroup122], (instregex "VSQRTSSr")>; + } // SchedModel |
