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authorDavid Majnemer <david.majnemer@gmail.com>2016-07-21 23:46:56 +0000
committerDavid Majnemer <david.majnemer@gmail.com>2016-07-21 23:46:56 +0000
commit1182dd8ed91d98e46e37cd33f7b8ba4ddbdc52ad (patch)
treeb0fcd393980d17661059a0f87e81fc7f07b96796 /llvm/lib/Target
parentf57f90dfd1c328fc8bb9d9009be0b7690a7bd761 (diff)
downloadbcm5719-llvm-1182dd8ed91d98e46e37cd33f7b8ba4ddbdc52ad.tar.gz
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[AArch64] Cleanup sign extend in genAlternativeCodeSequence
Use the machinery in MathExtras instead of rolling it by hand. This fixes PR28624. llvm-svn: 276366
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/AArch64/AArch64InstrInfo.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 0aa4708f35a..baaaf46d7fd 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -3462,7 +3462,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
unsigned Val = Root.getOperand(3).getImm();
Imm = Imm << Val;
}
- uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
+ uint64_t UImm = SignExtend64(Imm, BitSize);
uint64_t Encoding;
if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
MachineInstrBuilder MIB1 =
@@ -3548,12 +3548,12 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
RC = &AArch64::GPR64RegClass;
}
unsigned NewVR = MRI.createVirtualRegister(OrrRC);
- int Imm = Root.getOperand(2).getImm();
+ uint64_t Imm = Root.getOperand(2).getImm();
if (Root.getOperand(3).isImm()) {
unsigned Val = Root.getOperand(3).getImm();
Imm = Imm << Val;
}
- uint64_t UImm = -Imm << (64 - BitSize) >> (64 - BitSize);
+ uint64_t UImm = SignExtend64(-Imm, BitSize);
uint64_t Encoding;
if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
MachineInstrBuilder MIB1 =
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