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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-03-03 13:53:27 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-03-03 13:53:27 +0000 |
| commit | 11149ea4337c45505c438cb04b612fa228a0eee5 (patch) | |
| tree | 4c698d0ae3b7ddaad3f20268e03bfb80f271d856 /llvm/lib/Target | |
| parent | 24659eb2e7660ff7b6d06ed67fec091dbe56b70e (diff) | |
| download | bcm5719-llvm-11149ea4337c45505c438cb04b612fa228a0eee5.tar.gz bcm5719-llvm-11149ea4337c45505c438cb04b612fa228a0eee5.zip | |
[X86] Pull out combineToConsecutiveLoads helper. NFCI.
llvm-svn: 355287
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 40 |
1 files changed, 23 insertions, 17 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index fe2fd090e21..7aff9ab9b87 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -7466,6 +7466,26 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts, return SDValue(); } +// Combine a vector ops (shuffles etc.) that is equal to build_vector load1, +// load2, load3, load4, <0, 1, 2, 3> into a vector load if the load addresses +// are consecutive, non-overlapping, and in the right order. +static SDValue combineToConsecutiveLoads(EVT VT, SDNode *N, const SDLoc &DL, + SelectionDAG &DAG, + const X86Subtarget &Subtarget, + bool isAfterLegalize) { + SmallVector<SDValue, 64> Elts; + for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { + if (SDValue Elt = getShuffleScalarElt(N, i, DAG, 0)) { + Elts.push_back(Elt); + continue; + } + return SDValue(); + } + assert(Elts.size() == VT.getVectorNumElements()); + return EltsFromConsecutiveLoads(VT, Elts, DL, DAG, Subtarget, + isAfterLegalize); +} + static Constant *getConstantVector(MVT VT, const APInt &SplatValue, unsigned SplatBitSize, LLVMContext &C) { unsigned ScalarSize = VT.getScalarSizeInBits(); @@ -32762,23 +32782,9 @@ static SDValue combineShuffle(SDNode *N, SelectionDAG &DAG, } } - // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, - // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are - // consecutive, non-overlapping, and in the right order. - SmallVector<SDValue, 16> Elts; - for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { - if (SDValue Elt = getShuffleScalarElt(N, i, DAG, 0)) { - Elts.push_back(Elt); - continue; - } - Elts.clear(); - break; - } - - if (Elts.size() == VT.getVectorNumElements()) - if (SDValue LD = - EltsFromConsecutiveLoads(VT, Elts, dl, DAG, Subtarget, true)) - return LD; + // Attempt to combine into a vector load/broadcast. + if (SDValue LD = combineToConsecutiveLoads(VT, N, dl, DAG, Subtarget, true)) + return LD; // For AVX2, we sometimes want to combine // (vector_shuffle <mask> (concat_vectors t1, undef) |

