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| author | Craig Topper <craig.topper@intel.com> | 2019-09-05 18:49:52 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-05 18:49:52 +0000 |
| commit | 0fde412140ddbf8153a02e4d153c44398e441134 (patch) | |
| tree | ffc2544ef2622f1557017f8bfe0ec74510922074 /llvm/lib/Target | |
| parent | 07f967d94dd7eb9666e8c2d5f6e0f4e8a14919cd (diff) | |
| download | bcm5719-llvm-0fde412140ddbf8153a02e4d153c44398e441134.tar.gz bcm5719-llvm-0fde412140ddbf8153a02e4d153c44398e441134.zip | |
[X86] Enable BuildSDIVPow2 for i16.
We're able to use a 32-bit ADD and CMOV here and should work
well with our other i16->i32 promotion optimizations.
llvm-svn: 371107
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index d7efb0a126d..136d124ab4b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -20098,8 +20098,9 @@ X86TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor, // fold (sdiv X, pow2) EVT VT = N->getValueType(0); - // FIXME: Support i8/i16. - if ((VT != MVT::i32 && !(Subtarget.is64Bit() && VT == MVT::i64))) + // FIXME: Support i8. + if (VT != MVT::i16 && VT != MVT::i32 && + !(Subtarget.is64Bit() && VT == MVT::i64)) return SDValue(); unsigned Lg2 = Divisor.countTrailingZeros(); |
