diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-09-09 21:59:44 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-09-09 21:59:44 +0000 |
| commit | 0f2146bb5d59a407e111145bb1851f52450b8da2 (patch) | |
| tree | 307fcc40930233b0301c64c7750bf7dba8e467f8 /llvm/lib/Target | |
| parent | 712e78ee280a274feb708c6f933b3747095cf0aa (diff) | |
| download | bcm5719-llvm-0f2146bb5d59a407e111145bb1851f52450b8da2.tar.gz bcm5719-llvm-0f2146bb5d59a407e111145bb1851f52450b8da2.zip | |
I forgot that we always spill fp values as 64-bits. Implement spill folding
for FP as well. This triggers a couple dozen times on 177.mesa (for example).
llvm-svn: 23299
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp index 1ccc8599015..6d564b9ba41 100644 --- a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp @@ -149,14 +149,21 @@ MachineInstr *PPC32RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned InReg = MI->getOperand(1).getReg(); return addFrameReference(BuildMI(PPC::STW, 3).addReg(InReg), FrameIndex); - } else { + } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex); } } else if (Opc == PPC::FMR) { - // FIXME: We would be able to fold this, but we don't know whether to use a - // 32- or 64-bit load/store :(. + // We currently always spill FP values as doubles. :( + if (OpNum == 0) { // move -> store + unsigned InReg = MI->getOperand(1).getReg(); + return addFrameReference(BuildMI(PPC::STFD, + 3).addReg(InReg), FrameIndex); + } else { // move -> load + unsigned OutReg = MI->getOperand(0).getReg(); + return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex); + } } return 0; } |

