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authorSanjay Patel <spatel@rotateright.com>2015-08-10 17:00:44 +0000
committerSanjay Patel <spatel@rotateright.com>2015-08-10 17:00:44 +0000
commit0f12d71b496ee62f879e432165c8871d3cad6712 (patch)
tree2ced6ccbfa7ae2a530ced13570ef1554916c9902 /llvm/lib/Target
parent08142fa6c7d63ad0a822e1e572a9c86478ba2737 (diff)
downloadbcm5719-llvm-0f12d71b496ee62f879e432165c8871d3cad6712.tar.gz
bcm5719-llvm-0f12d71b496ee62f879e432165c8871d3cad6712.zip
fix minsize detection: minsize attribute implies optimizing for size
llvm-svn: 244463
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp5
1 files changed, 1 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index b6f34bd3a18..6dd4fb8d98e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -24127,10 +24127,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
return SDValue();
// fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
- MachineFunction &MF = DAG.getMachineFunction();
- // FIXME: Use Function::optForSize().
- bool OptForSize =
- MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
+ bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
// SHLD/SHRD instructions have lower register pressure, but on some
// platforms they have higher latency than the equivalent
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