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| author | Craig Topper <craig.topper@intel.com> | 2017-11-11 02:26:05 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-11-11 02:26:05 +0000 |
| commit | 0eb4a4338451fb674c0b0be83fdcda4639e250c8 (patch) | |
| tree | 87062f008b40add6fa0ef34eeea4bc90978ae89d /llvm/lib/Target | |
| parent | bf9b944ea760f10a26d2b1455c24911438660828 (diff) | |
| download | bcm5719-llvm-0eb4a4338451fb674c0b0be83fdcda4639e250c8.tar.gz bcm5719-llvm-0eb4a4338451fb674c0b0be83fdcda4639e250c8.zip | |
[X86] Correct the execution domain on ROUND/VROUND instructions.
llvm-svn: 317968
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index e7986bf1b0d..a9bae9bd188 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -5829,7 +5829,7 @@ let ExeDomain = SSEPackedDouble in { multiclass avx_fp_unop_rm<bits<8> opcss, bits<8> opcsd, string OpcodeStr> { -let ExeDomain = GenericDomain, hasSideEffects = 0 in { +let ExeDomain = SSEPackedSingle, hasSideEffects = 0 in { def SSr : SS4AIi8<opcss, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3), !strconcat(OpcodeStr, @@ -5842,7 +5842,9 @@ let ExeDomain = GenericDomain, hasSideEffects = 0 in { !strconcat(OpcodeStr, "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>, Sched<[WriteFAddLd, ReadAfterLd]>; +} // ExeDomain = SSEPackedSingle, hasSideEffects = 0 +let ExeDomain = SSEPackedDouble, hasSideEffects = 0 in { def SDr : SS4AIi8<opcsd, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3), !strconcat(OpcodeStr, @@ -5855,12 +5857,12 @@ let ExeDomain = GenericDomain, hasSideEffects = 0 in { !strconcat(OpcodeStr, "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>, Sched<[WriteFAddLd, ReadAfterLd]>; -} // ExeDomain = GenericDomain, hasSideEffects = 0 +} // ExeDomain = SSEPackedDouble, hasSideEffects = 0 } multiclass sse41_fp_unop_s<bits<8> opcss, bits<8> opcsd, string OpcodeStr> { -let ExeDomain = GenericDomain, hasSideEffects = 0 in { +let ExeDomain = SSEPackedSingle, hasSideEffects = 0 in { def SSr : SS4AIi8<opcss, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, i32u8imm:$src2), !strconcat(OpcodeStr, @@ -5873,7 +5875,9 @@ let ExeDomain = GenericDomain, hasSideEffects = 0 in { !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, Sched<[WriteFAddLd, ReadAfterLd]>; +} // ExeDomain = SSEPackedSingle, hasSideEffects = 0 +let ExeDomain = SSEPackedDouble, hasSideEffects = 0 in { def SDr : SS4AIi8<opcsd, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, i32u8imm:$src2), !strconcat(OpcodeStr, @@ -5886,14 +5890,14 @@ let ExeDomain = GenericDomain, hasSideEffects = 0 in { !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, Sched<[WriteFAddLd, ReadAfterLd]>; -} // ExeDomain = GenericDomain, hasSideEffects = 0 +} // ExeDomain = SSEPackedDouble, hasSideEffects = 0 } multiclass sse41_fp_binop_s<bits<8> opcss, bits<8> opcsd, string OpcodeStr, Intrinsic F32Int, Intrinsic F64Int, bit Is2Addr = 1> { -let ExeDomain = GenericDomain, isCodeGenOnly = 1 in { +let ExeDomain = SSEPackedSingle, isCodeGenOnly = 1 in { def SSr_Int : SS4AIi8<opcss, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3), !if(Is2Addr, @@ -5914,7 +5918,9 @@ let ExeDomain = GenericDomain, isCodeGenOnly = 1 in { [(set VR128:$dst, (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>, Sched<[WriteFAddLd, ReadAfterLd]>; +} // ExeDomain = SSEPackedSingle, isCodeGenOnly = 1 +let ExeDomain = SSEPackedDouble, isCodeGenOnly = 1 in { def SDr_Int : SS4AIi8<opcsd, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3), !if(Is2Addr, @@ -5935,7 +5941,7 @@ let ExeDomain = GenericDomain, isCodeGenOnly = 1 in { [(set VR128:$dst, (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>, Sched<[WriteFAddLd, ReadAfterLd]>; -} // ExeDomain = GenericDomain, isCodeGenOnly = 1 +} // ExeDomain = SSEPackedDouble, isCodeGenOnly = 1 } // FP round - roundss, roundps, roundsd, roundpd |
