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authorCraig Topper <craig.topper@gmail.com>2012-07-20 07:03:46 +0000
committerCraig Topper <craig.topper@gmail.com>2012-07-20 07:03:46 +0000
commit0b94e46ce3854eab383ea212973c9ffcdbead65e (patch)
tree5c6309aace9f394463faf32c8d3b24770f75fc16 /llvm/lib/Target
parentcd8a546b6c18f7484b493b28cdafaa23fe7074ac (diff)
downloadbcm5719-llvm-0b94e46ce3854eab383ea212973c9ffcdbead65e.tar.gz
bcm5719-llvm-0b94e46ce3854eab383ea212973c9ffcdbead65e.zip
Don't use implicit register operands to calculate L-bit for AVX instructions. Needed because super reg defs and kills are added as implicit operands on 128-bit instructions. Fixes PR13349. Patch by Jose Fonseca.
llvm-svn: 160543
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/X86/X86CodeEmitter.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86CodeEmitter.cpp b/llvm/lib/Target/X86/X86CodeEmitter.cpp
index 977cc50c139..d7050495f89 100644
--- a/llvm/lib/Target/X86/X86CodeEmitter.cpp
+++ b/llvm/lib/Target/X86/X86CodeEmitter.cpp
@@ -927,6 +927,8 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
if (!MI.getOperand(i).isReg())
continue;
+ if (MI.getOperand(i).isImplicit())
+ continue;
unsigned SrcReg = MI.getOperand(i).getReg();
if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
VEX_L = 1;
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