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| author | Chad Rosier <mcrosier@codeaurora.org> | 2016-05-13 22:53:13 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2016-05-13 22:53:13 +0000 |
| commit | 08d9908ea998ca84321be9e52830b3783d760e5b (patch) | |
| tree | 4a42182051f225f0642751dd25b84a3b9407c4d9 /llvm/lib/Target | |
| parent | 99223441780875a5bc72823701c3170b01647f9a (diff) | |
| download | bcm5719-llvm-08d9908ea998ca84321be9e52830b3783d760e5b.tar.gz bcm5719-llvm-08d9908ea998ca84321be9e52830b3783d760e5b.zip | |
[AArch64] Simplify logic to reduce vertical space. NFC.
llvm-svn: 269512
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index c433b2b5a31..6d1b95eccf7 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -2110,12 +2110,7 @@ bool AArch64DAGToDAGISel::tryBitfieldInsertInZeroOp(SDNode *N) { return false; EVT VT = N->getValueType(0); - unsigned Opc; - if (VT == MVT::i32) - Opc = AArch64::UBFMWri; - else if (VT == MVT::i64) - Opc = AArch64::UBFMXri; - else + if (VT != MVT::i32 && VT != MVT::i64) return false; SDValue Op0; @@ -2132,6 +2127,7 @@ bool AArch64DAGToDAGISel::tryBitfieldInsertInZeroOp(SDNode *N) { SDLoc DL(N); SDValue Ops[] = {Op0, CurDAG->getTargetConstant(ImmR, DL, VT), CurDAG->getTargetConstant(ImmS, DL, VT)}; + unsigned Opc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri; CurDAG->SelectNodeTo(N, Opc, VT, Ops); return true; } |
