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| author | David Green <david.green@arm.com> | 2019-04-10 18:00:41 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2019-04-10 18:00:41 +0000 |
| commit | 0861c87b06c5573d919ec550bbbd2a1624d22ba0 (patch) | |
| tree | 99fec9561f6122cd38721bf5947e097a61ad7348 /llvm/lib/Target | |
| parent | 5f6eb1817af8d525ee93ac8a1f0cf9c881b3ebd3 (diff) | |
| download | bcm5719-llvm-0861c87b06c5573d919ec550bbbd2a1624d22ba0.tar.gz bcm5719-llvm-0861c87b06c5573d919ec550bbbd2a1624d22ba0.zip | |
Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg
Certain optimisations from ConstantHoisting and CGP rely on Selection DAG not
seeing through to the constant in other blocks. Revert this patch while we come
up with a better way to handle that.
I will try to follow this up with some better tests.
llvm-svn: 358113
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 2f5db87090e..190d5708324 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -19595,10 +19595,10 @@ static SDValue LowerAndToBT(SDValue And, ISD::CondCode CC, DAG.MaskedValueIsZero(BitNo, APInt(BitNo.getValueSizeInBits(), 32))) Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src); - // If the operand types disagree, extend or truncate the shift amount to match. - // Since BT ignores high bits (like shifts) we can use anyextend for the extension. + // If the operand types disagree, extend the shift amount to match. Since + // BT ignores high bits (like shifts) we can use anyextend. if (Src.getValueType() != BitNo.getValueType()) - BitNo = DAG.getAnyExtOrTrunc(BitNo, dl, Src.getValueType()); + BitNo = DAG.getNode(ISD::ANY_EXTEND, dl, Src.getValueType(), BitNo); X86CC = DAG.getConstant(CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B, dl, MVT::i8); |

