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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-22 18:35:53 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-22 18:35:53 +0000 |
| commit | 06e16541ba695ad3fd39f4d646a55a08482b096b (patch) | |
| tree | 6e61f0c10dfb6bbc06e500a61b03f6264a90c69c /llvm/lib/Target | |
| parent | 091680b6e70cad1f0088f733761a222f6b58efaf (diff) | |
| download | bcm5719-llvm-06e16541ba695ad3fd39f4d646a55a08482b096b.tar.gz bcm5719-llvm-06e16541ba695ad3fd39f4d646a55a08482b096b.zip | |
[X86] Remove unnecessary WriteFBlend/WriteBlend InstRW overrides.
Fixed a lot of the default classes which were being completely overridden.
llvm-svn: 330554
Diffstat (limited to 'llvm/lib/Target')
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedBroadwell.td | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSkylakeClient.td | 10 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 15 |
5 files changed, 12 insertions, 34 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 4f2655dbe40..cb366ef38ec 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -185,7 +185,7 @@ defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // PMULLD defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles. defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1>; // Vector variable shuffles. -defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends. +defm : BWWriteResPair<WriteBlend, [BWPort5], 1>; // Vector blends. defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2], 2, 5>; // Vector variable blends. defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD. defm : BWWriteResPair<WritePSADBW, [BWPort0], 5>; // Vector PSADBW. @@ -353,7 +353,6 @@ def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr", "MMX_MOVQ2DQrr", "(V?)MOV64toPQIrr", "(V?)MOVDI2PDIrr", - "(V?)PBLENDW(Y?)rri", "(V?)PSLLDQ(Y?)ri", "(V?)PSRLDQ(Y?)ri")>; @@ -1003,7 +1002,6 @@ def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi", "(V?)PACKUSDWrm", "(V?)PACKUSWBrm", "(V?)PALIGNRrmi", - "(V?)PBLENDWrmi", "VPERMILPDmi", "VPERMILPDrm", "VPERMILPSmi", @@ -1121,9 +1119,7 @@ def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[BWWriteResGroup65], (instregex "(V?)BLENDPDrmi", - "(V?)BLENDPSrmi", - "VINSERTF128rm", +def: InstRW<[BWWriteResGroup65], (instregex "VINSERTF128rm", "VINSERTI128rm", "VPBLENDDrmi")>; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 7aa834736d6..e11e380a3ef 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -164,7 +164,7 @@ defm : HWWriteResPair<WriteFSign, [HWPort0], 1>; defm : HWWriteResPair<WriteFLogic, [HWPort5], 1, [1], 1, 6>; defm : HWWriteResPair<WriteFShuffle, [HWPort5], 1>; defm : HWWriteResPair<WriteFVarShuffle, [HWPort5], 1>; -defm : HWWriteResPair<WriteFBlend, [HWPort015], 1>; +defm : HWWriteResPair<WriteFBlend, [HWPort015], 1, [1], 1, 6>; defm : HWWriteResPair<WriteFShuffle256, [HWPort5], 3>; defm : HWWriteResPair<WriteFVarShuffle256, [HWPort5], 3>; defm : HWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2], 2, 6>; @@ -181,7 +181,7 @@ defm : HWWriteResPair<WriteVecIMul, [HWPort0], 5>; defm : HWWriteResPair<WritePMULLD, [HWPort0], 10, [2], 2, 6>; defm : HWWriteResPair<WriteShuffle, [HWPort5], 1>; defm : HWWriteResPair<WriteVarShuffle, [HWPort5], 1>; -defm : HWWriteResPair<WriteBlend, [HWPort15], 1>; +defm : HWWriteResPair<WriteBlend, [HWPort5], 1, [1], 1, 6>; defm : HWWriteResPair<WriteShuffle256, [HWPort5], 3>; defm : HWWriteResPair<WriteVarShuffle256, [HWPort5], 3>; defm : HWWriteResPair<WriteVarBlend, [HWPort5], 2, [2], 2, 6>; @@ -695,7 +695,6 @@ def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr", "MMX_MOVQ2DQrr", "(V?)MOV64toPQIrr", "(V?)MOVDI2PDIrr", - "(V?)PBLENDW(Y?)rri", "(V?)PSLLDQ(Y?)ri", "(V?)PSRLDQ(Y?)ri")>; @@ -872,7 +871,6 @@ def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKLWDrm", "(V?)PACKUSDWrm", "(V?)PACKUSWBrm", "(V?)PALIGNRrmi", - "(V?)PBLENDWrmi", "VPERMILPDmi", "VPERMILPDrm", "VPERMILPSmi", @@ -1109,9 +1107,7 @@ def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[HWWriteResGroup17], (instregex "(V?)BLENDPDrmi", - "(V?)BLENDPSrmi", - "VINSERTF128rm", +def: InstRW<[HWWriteResGroup17], (instregex "VINSERTF128rm", "VINSERTI128rm", "VPBLENDDrmi")>; diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index c4dd583d409..3d2d495c5f0 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -168,7 +168,7 @@ defm : SBWriteResPair<WriteVecIMul, [SBPort0], 5>; defm : SBWriteResPair<WritePMULLD, [SBPort0], 5, [1], 1, 6>; // TODO this is probably wrong for 256/512-bit for the "generic" model defm : SBWriteResPair<WriteShuffle, [SBPort5], 1>; defm : SBWriteResPair<WriteVarShuffle, [SBPort15], 1>; -defm : SBWriteResPair<WriteBlend, [SBPort15], 1>; +defm : SBWriteResPair<WriteBlend, [SBPort15], 1, [1], 1, 6>; defm : SBWriteResPair<WriteVarBlend, [SBPort15], 2, [2], 2, 6>; defm : SBWriteResPair<WriteMPSAD, [SBPort0, SBPort15], 7, [1,2], 3, 6>; defm : SBWriteResPair<WritePSADBW, [SBPort0], 5>; @@ -1012,7 +1012,6 @@ def: InstRW<[SBWriteResGroup59], (instregex "MMX_PADDQirm", "(V?)PALIGNRrmi", "(V?)PAVGBrm", "(V?)PAVGWrm", - "(V?)PBLENDWrmi", "(V?)PCMPEQBrm", "(V?)PCMPEQDrm", "(V?)PCMPEQQrm", diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 7024e1dd52e..8e9108f1967 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -164,7 +164,7 @@ defm : SKLWriteResPair<WriteFSign, [SKLPort0], 1>; // Floating point fabs/fchs defm : SKLWriteResPair<WriteFLogic, [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1>; // Floating point vector shuffles. defm : SKLWriteResPair<WriteFVarShuffle, [SKLPort5], 1>; // Floating point vector shuffles. -defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1>; // Floating point vector blends. +defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends. defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends. // FMA Scheduling helper class. @@ -182,7 +182,7 @@ defm : SKLWriteResPair<WriteVecIMul, [SKLPort0], 5>; // Vector integer multip defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>; defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1>; // Vector shuffles. defm : SKLWriteResPair<WriteVarShuffle, [SKLPort5], 1>; // Vector shuffles. -defm : SKLWriteResPair<WriteBlend, [SKLPort15], 1>; // Vector blends. +defm : SKLWriteResPair<WriteBlend, [SKLPort5], 1, [1], 1, 6>; // Vector blends. defm : SKLWriteResPair<WriteVarBlend, [SKLPort015], 2, [2], 2, 6>; // Vector variable blends. defm : SKLWriteResPair<WriteMPSAD, [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD. defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3>; // Vector PSADBW. @@ -364,7 +364,6 @@ def: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r", "UCOM_Fr", "(V?)MOV64toPQIrr", "(V?)MOVDI2PDIrr", - "(V?)PBLENDW(Y?)rri", "(V?)PSLLDQ(Y?)ri", "(V?)PSRLDQ(Y?)ri")>; @@ -1339,7 +1338,6 @@ def: InstRW<[SKLWriteResGroup88], (instregex "(V?)INSERTPSrm", "(V?)PACKUSDWrm", "(V?)PACKUSWBrm", "(V?)PALIGNRrmi", - "(V?)PBLENDWrmi", "VPBROADCASTBrm", "VPBROADCASTWrm", "VPERMILPDmi", @@ -1436,9 +1434,7 @@ def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKLWriteResGroup91], (instregex "(V?)BLENDPDrmi", - "(V?)BLENDPSrmi", - "(V?)INSERTF128rm", +def: InstRW<[SKLWriteResGroup91], (instregex "(V?)INSERTF128rm", "(V?)INSERTI128rm", "(V?)MASKMOVPDrm", "(V?)MASKMOVPSrm", diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 561e4ebea99..d6d89f107e6 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -164,7 +164,7 @@ defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs. defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1>; // Floating point vector shuffles. defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1>; // Floating point vector variable shuffles. -defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1>; // Floating point vector blends. +defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends. defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends. // FMA Scheduling helper class. @@ -182,7 +182,7 @@ defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 5>; // Vector integer multip defm : SKXWriteResPair<WritePMULLD, [SKXPort015], 10, [2], 2, 6>; // Vector integer multiply. defm : SKXWriteResPair<WriteShuffle, [SKXPort5], 1>; // Vector shuffles. defm : SKXWriteResPair<WriteVarShuffle, [SKXPort5], 1>; // Vector variable shuffles. -defm : SKXWriteResPair<WriteBlend, [SKXPort15], 1>; // Vector blends. +defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends. defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends. defm : SKXWriteResPair<WriteMPSAD, [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD. defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3, [1,1], 1, 6>; // Vector PSADBW. @@ -406,7 +406,6 @@ def: InstRW<[SKXWriteResGroup3], (instregex "COMP_FST0r", "MMX_MOVD64to64rr", "MOV64toPQIrr", "MOVDI2PDIrr", - "PBLENDWrri", "PSLLDQri", "PSRLDQri", "UCOM_FPr", @@ -415,8 +414,6 @@ def: InstRW<[SKXWriteResGroup3], (instregex "COMP_FST0r", "VMOV64toPQIrr", "VMOVDI2PDIZrr", "VMOVDI2PDIrr", - "VPBLENDWYrri", - "VPBLENDWrri", "VPSLLDQYri", "VPSLLDQZ128rr", "VPSLLDQZ256rr", @@ -2516,7 +2513,6 @@ def: InstRW<[SKXWriteResGroup92], (instregex "INSERTPSrm", "PACKUSDWrm", "PACKUSWBrm", "PALIGNRrmi", - "PBLENDWrmi", "PSHUFBrm", "PSHUFDmi", "PSHUFHWmi", @@ -2549,7 +2545,6 @@ def: InstRW<[SKXWriteResGroup92], (instregex "INSERTPSrm", "VPACKUSWBrm", "VPALIGNRZ128rmi(b?)", "VPALIGNRrmi", - "VPBLENDWrmi", "VPBROADCASTBZ128m(b?)", "VPBROADCASTBrm", "VPBROADCASTWZ128m(b?)", @@ -2808,9 +2803,7 @@ def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKXWriteResGroup95], (instregex "BLENDPDrmi", - "BLENDPSrmi", - "PADDBrm", +def: InstRW<[SKXWriteResGroup95], (instregex "PADDBrm", "PADDDrm", "PADDQrm", "PADDWrm", @@ -2820,8 +2813,6 @@ def: InstRW<[SKXWriteResGroup95], (instregex "BLENDPDrmi", "PSUBWrm", "VBLENDMPDZ128rm(b?)", "VBLENDMPSZ128rm(b?)", - "VBLENDPDrmi", - "VBLENDPSrmi", "VBROADCASTI32X2Z128m(b?)", "VBROADCASTSSZ128m(b?)", "VINSERTF128rm", |

