summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
diff options
context:
space:
mode:
authorAna Pazos <apazos@codeaurora.org>2018-09-13 18:37:23 +0000
committerAna Pazos <apazos@codeaurora.org>2018-09-13 18:37:23 +0000
commit065b088759c2f3b1e92743008fd0a6eed3ff5290 (patch)
treedf11f1d7014a54186fa7ea29243ad9f8c21f5796 /llvm/lib/Target
parentb0799dda77c6b75526e1415331e2a9656abd6f95 (diff)
downloadbcm5719-llvm-065b088759c2f3b1e92743008fd0a6eed3ff5290.tar.gz
bcm5719-llvm-065b088759c2f3b1e92743008fd0a6eed3ff5290.zip
[RISCV][MC] Reject bare symbols for the simm6 and simm6nonzero operand types
Summary: Fixed assertions due to invalid fixup when encoding compressed instructions (c.addi, c.addiw, c.li, c.andi) with bare symbols with/without modifiers. This matches GAS behavior as well. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D52005 llvm-svn: 342160
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp18
1 files changed, 4 insertions, 14 deletions
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 3e469c89369..7b010f54b0b 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -326,14 +326,9 @@ public:
return false;
RISCVMCExpr::VariantKind VK;
int64_t Imm;
- bool IsValid;
bool IsConstantImm = evaluateConstantImm(Imm, VK);
- if (!IsConstantImm)
- IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm);
- else
- IsValid = isInt<6>(Imm);
- return IsValid &&
- (VK == RISCVMCExpr::VK_RISCV_None || VK == RISCVMCExpr::VK_RISCV_LO);
+ return IsConstantImm && isInt<6>(Imm) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
}
bool isSImm6NonZero() const {
@@ -341,14 +336,9 @@ public:
return false;
RISCVMCExpr::VariantKind VK;
int64_t Imm;
- bool IsValid;
bool IsConstantImm = evaluateConstantImm(Imm, VK);
- if (!IsConstantImm)
- IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm);
- else
- IsValid = ((Imm != 0) && isInt<6>(Imm));
- return IsValid &&
- (VK == RISCVMCExpr::VK_RISCV_None || VK == RISCVMCExpr::VK_RISCV_LO);
+ return IsConstantImm && isInt<6>(Imm) && (Imm != 0) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
}
bool isCLUIImm() const {
OpenPOWER on IntegriCloud