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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2015-10-28 13:54:36 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2015-10-28 13:54:36 +0000 |
| commit | 039b10423ab1eea6ea54dc37169f811c238ee559 (patch) | |
| tree | 678d0e5e77794872bacb92b7a66dbc9e08da4c4b /llvm/lib/Target | |
| parent | e003ca2a03b2b4d776628183c988f0e15c44240c (diff) | |
| download | bcm5719-llvm-039b10423ab1eea6ea54dc37169f811c238ee559.tar.gz bcm5719-llvm-039b10423ab1eea6ea54dc37169f811c238ee559.zip | |
Put global classes into the appropriate namespace.
Most of the cases belong into an anonymous namespace. No
functionality change intended.
llvm-svn: 251515
Diffstat (limited to 'llvm/lib/Target')
4 files changed, 9 insertions, 6 deletions
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp index 41112ac0b46..45e1909ede5 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp @@ -27,6 +27,7 @@ using namespace llvm; +namespace { // Insn shuffling priority. class HexagonBid { // The priority is directly proportional to how restricted the insn is based @@ -75,6 +76,7 @@ public: return false; }; }; +} // end anonymous namespace unsigned HexagonResource::setWeight(unsigned s) { const unsigned SlotWeight = 8; diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 05ae449028c..78c3e224a00 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -2094,8 +2094,7 @@ bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, } /// Can the value be represented by a unsigned N-bit value and a shift left? -template<unsigned N> -bool isShiftedUIntAtAnyPosition(uint64_t x) { +template <unsigned N> static bool isShiftedUIntAtAnyPosition(uint64_t x) { unsigned BitNum = findFirstSet(x); return (x == x >> BitNum << BitNum) && isUInt<N>(x >> BitNum); diff --git a/llvm/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp b/llvm/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp index 059ae3f7fb0..6444cf8e464 100644 --- a/llvm/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp +++ b/llvm/lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp @@ -60,15 +60,15 @@ void SystemZInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const { O << '%' << getRegisterName(RegNo); } -template<unsigned N> -void printUImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { +template <unsigned N> +static void printUImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { int64_t Value = MI->getOperand(OpNum).getImm(); assert(isUInt<N>(Value) && "Invalid uimm argument"); O << Value; } -template<unsigned N> -void printSImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { +template <unsigned N> +static void printSImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { int64_t Value = MI->getOperand(OpNum).getImm(); assert(isInt<N>(Value) && "Invalid simm argument"); O << Value; diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index e920450732e..63929b189ee 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -95,11 +95,13 @@ X86GenericDisassembler::X86GenericDisassembler( llvm_unreachable("Invalid CPU mode"); } +namespace { struct Region { ArrayRef<uint8_t> Bytes; uint64_t Base; Region(ArrayRef<uint8_t> Bytes, uint64_t Base) : Bytes(Bytes), Base(Base) {} }; +} // end anonymous namespace /// A callback function that wraps the readByte method from Region. /// |

