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| author | Torok Edwin <edwintorok@gmail.com> | 2009-10-19 11:00:58 +0000 |
|---|---|---|
| committer | Torok Edwin <edwintorok@gmail.com> | 2009-10-19 11:00:58 +0000 |
| commit | 033f01c9224d91f893fdcd0372d3a4795b4e3b89 (patch) | |
| tree | aebe041449fe94d930c84b5d9327bdd3ff4aba6f /llvm/lib/Target | |
| parent | b625a13c7979759eccf3fc40c383b8a6601f96d6 (diff) | |
| download | bcm5719-llvm-033f01c9224d91f893fdcd0372d3a4795b4e3b89.tar.gz bcm5719-llvm-033f01c9224d91f893fdcd0372d3a4795b4e3b89.zip | |
Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS.
LLC was scheduling compares before the adds causing wrong branches to be taken
in programs, resulting in misoptimized code wherever atomic adds where used.
llvm-svn: 84485
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86Instr64bit.td | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86Instr64bit.td b/llvm/lib/Target/X86/X86Instr64bit.td index ef19823a283..f7d5ef275fe 100644 --- a/llvm/lib/Target/X86/X86Instr64bit.td +++ b/llvm/lib/Target/X86/X86Instr64bit.td @@ -1515,6 +1515,7 @@ def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val) } // Optimized codegen when the non-memory output is not used. +let Defs = [EFLAGS] in { // FIXME: Use normal add / sub instructions and add lock prefix dynamically. def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), "lock\n\t" @@ -1544,7 +1545,7 @@ def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "lock\n\t" "dec{q}\t$dst", []>, LOCK; - +} // Atomic exchange, and, or, xor let Constraints = "$val = $dst", Defs = [EFLAGS], usesCustomDAGSchedInserter = 1 in { |
