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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-11-18 13:53:34 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-11-18 13:53:34 +0000 |
| commit | 01e65d2cfc537d9163af6fd1a282868c41bae3fc (patch) | |
| tree | 76ba70b9cc2dd71e9533736aa6c45f612dfe114c /llvm/lib/Target | |
| parent | 77382be56b3f1ff11cb7e44e6cccb0f429781e01 (diff) | |
| download | bcm5719-llvm-01e65d2cfc537d9163af6fd1a282868c41bae3fc.tar.gz bcm5719-llvm-01e65d2cfc537d9163af6fd1a282868c41bae3fc.zip | |
AMDGPU/SI: Remove zero_extend patterns for i16 ops selected to 32-bit insts
Summary:
The 32-bit instructions don't zero the high 16-bits like the 16-bit
instructions do.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D26828
llvm-svn: 287342
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP2Instructions.td | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index b87f3be2139..dec133c09ca 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -424,9 +424,20 @@ defm : Arithmetic_i16_Pats<smax, V_MAX_I16_e32>; defm : Arithmetic_i16_Pats<umin, V_MIN_U16_e32>; defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e32>; -defm : Arithmetic_i16_Pats<and, V_AND_B32_e32>; -defm : Arithmetic_i16_Pats<or, V_OR_B32_e32>; -defm : Arithmetic_i16_Pats<xor, V_XOR_B32_e32>; +def : Pat < + (and i16:$src0, i16:$src1), + (V_AND_B32_e32 $src0, $src1) +>; + +def : Pat < + (or i16:$src0, i16:$src1), + (V_OR_B32_e32 $src0, $src1) +>; + +def : Pat < + (xor i16:$src0, i16:$src1), + (V_XOR_B32_e32 $src0, $src1) +>; defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e32>; defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e32>; |
