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| author | Kerry McLaughlin <kerry.mclaughlin@arm.com> | 2019-09-30 17:10:21 +0000 |
|---|---|---|
| committer | Kerry McLaughlin <kerry.mclaughlin@arm.com> | 2019-09-30 17:10:21 +0000 |
| commit | 01b84e175c500dd85c522920de992c0b2c5b1060 (patch) | |
| tree | ba0a997f957797ed02077bdc259dc0083d50c538 /llvm/lib/Target | |
| parent | 8299fd9dee7df7c5f92ab2572aad04ce2fbbf83e (diff) | |
| download | bcm5719-llvm-01b84e175c500dd85c522920de992c0b2c5b1060.tar.gz bcm5719-llvm-01b84e175c500dd85c522920de992c0b2c5b1060.zip | |
[AArch64][SVE] Implement punpk[hi|lo] intrinsics
Summary:
Adds the following two intrinsics:
- int_aarch64_sve_punpkhi
- int_aarch64_sve_punpklo
This patch also contains a fix which allows LLVMHalfElementsVectorType
to forward reference overloadable arguments.
Reviewers: sdesmalen, rovka, rengolin
Reviewed By: sdesmalen
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, greened, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67830
llvm-svn: 373232
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 13 |
2 files changed, 15 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 0813c41dc66..cdf313db1b9 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -216,8 +216,8 @@ let Predicates = [HasSVE] in { defm UUNPKLO_ZZ : sve_int_perm_unpk<0b10, "uunpklo">; defm UUNPKHI_ZZ : sve_int_perm_unpk<0b11, "uunpkhi">; - def PUNPKLO_PP : sve_int_perm_punpk<0b0, "punpklo">; - def PUNPKHI_PP : sve_int_perm_punpk<0b1, "punpkhi">; + defm PUNPKLO_PP : sve_int_perm_punpk<0b0, "punpklo", int_aarch64_sve_punpklo>; + defm PUNPKHI_PP : sve_int_perm_punpk<0b1, "punpkhi", int_aarch64_sve_punpkhi>; defm MOVPRFX_ZPzZ : sve_int_movprfx_pred_zero<0b000, "movprfx">; defm MOVPRFX_ZPmZ : sve_int_movprfx_pred_merge<0b001, "movprfx">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 8c8713b464e..f57e111b7e1 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -283,6 +283,11 @@ let Predicates = [HasSVE] in { // SVE pattern match helpers. //===----------------------------------------------------------------------===// +class SVE_1_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1, + Instruction inst> +: Pat<(vtd (op vt1:$Op1)), + (inst $Op1)>; + class SVE_3_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1, ValueType vt2, ValueType vt3, Instruction inst> : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)), @@ -4280,6 +4285,14 @@ class sve_int_perm_punpk<bit opc, string asm> let Inst{3-0} = Pd; } +multiclass sve_int_perm_punpk<bit opc, string asm, SDPatternOperator op> { + def NAME : sve_int_perm_punpk<opc, asm>; + + def : SVE_1_Op_Pat<nxv8i1, op, nxv16i1, !cast<Instruction>(NAME)>; + def : SVE_1_Op_Pat<nxv4i1, op, nxv8i1, !cast<Instruction>(NAME)>; + def : SVE_1_Op_Pat<nxv2i1, op, nxv4i1, !cast<Instruction>(NAME)>; +} + class sve_int_rdffr_pred<bit s, string asm> : I<(outs PPR8:$Pd), (ins PPRAny:$Pg), asm, "\t$Pd, $Pg/z", |
