Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.

llvm-svn: 30844

6 files changed, 72 insertions, 83 deletions

diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 785af30e3a7..d5172566a7c 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -346,9 +346,9 @@ void X86DAGToDAGISel::InstructionSelectPreprocess(SelectionDAG &DAG) {
       case ISD::ADDE: {
         SDOperand N10 = N1.getOperand(0);
         SDOperand N11 = N1.getOperand(1);
-        if (N10.Val->getOpcode() == ISD::LOAD)
+        if (ISD::isNON_EXTLoad(N10.Val))
           RModW = true;
-        else if (N11.Val->getOpcode() == ISD::LOAD) {
+        else if (ISD::isNON_EXTLoad(N11.Val)) {
           RModW = true;
           std::swap(N10, N11);
         }
@@ -370,7 +370,7 @@ void X86DAGToDAGISel::InstructionSelectPreprocess(SelectionDAG &DAG) {
       case X86ISD::SHLD:
       case X86ISD::SHRD: {
         SDOperand N10 = N1.getOperand(0);
-        if (N10.Val->getOpcode() == ISD::LOAD)
+        if (ISD::isNON_EXTLoad(N10.Val))
           RModW = N10.Val->isOperand(Chain.Val) && N10.hasOneUse() &&
             (N10.getOperand(1) == N2) &&
             (N10.Val->getValueType(0) == N1.getValueType());
@@ -806,7 +806,7 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base,
 bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
                                   SDOperand &Base, SDOperand &Scale,
                                   SDOperand &Index, SDOperand &Disp) {
-  if (N.getOpcode() == ISD::LOAD &&
+  if (ISD::isNON_EXTLoad(N.Val) &&
       N.hasOneUse() &&
       CanBeFoldedBy(N.Val, P.Val))
     return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index cd8fba9ef9d..7abfc58d00d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -490,8 +490,7 @@ SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
       // Create the frame index object for this incoming parameter...
       int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
       SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
-      ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
-                             DAG.getSrcValue(NULL));
+      ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
       ArgValues.push_back(ArgValue);
       ArgOffset += ArgIncrement;   // Move on to the next argument...
     }
@@ -763,8 +762,7 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) {
       Ops.push_back(DAG.getValueType(RetVT));
       Ops.push_back(InFlag);
       Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
-      RetVal = DAG.getLoad(RetVT, Chain, StackSlot,
-                           DAG.getSrcValue(NULL));
+      RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0);
       Chain = RetVal.getValue(1);
     }
 
@@ -963,8 +961,7 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
       // parameter.
       int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
       SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
-      ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
-                             DAG.getSrcValue(NULL));
+      ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
       ArgOffset += ArgIncrement;   // Move on to the next argument.
     }
 
@@ -1470,11 +1467,10 @@ X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
       SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
       if (ObjectVT == MVT::i64 && ObjIntRegs) {
         SDOperand ArgValue2 = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
-                                          DAG.getSrcValue(NULL));
+                                          NULL, 0);
         ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
       } else
-        ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
-                               DAG.getSrcValue(NULL));
+        ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
       ArgOffset += ArgIncrement;   // Move on to the next argument.
     }
 
@@ -1800,8 +1796,7 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
       Ops.push_back(DAG.getValueType(RetVT));
       Ops.push_back(InFlag);
       Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
-      RetVal = DAG.getLoad(RetVT, Chain, StackSlot,
-                           DAG.getSrcValue(NULL));
+      RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0);
       Chain = RetVal.getValue(1);
     }
 
@@ -1880,8 +1875,7 @@ SDOperand X86TargetLowering::LowerStdCallCCArguments(SDOperand Op,
     // Create the frame index object for this incoming parameter...
     int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
     SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
-    ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
-                           DAG.getSrcValue(NULL));
+    ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
     ArgValues.push_back(ArgValue);
     ArgOffset += ArgIncrement;   // Move on to the next argument...
   }
@@ -2086,8 +2080,7 @@ SDOperand X86TargetLowering::LowerStdCallCCCallTo(SDOperand Op,
       Ops.push_back(DAG.getValueType(RetVT));
       Ops.push_back(InFlag);
       Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
-      RetVal = DAG.getLoad(RetVT, Chain, StackSlot,
-                           DAG.getSrcValue(NULL));
+      RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0);
       Chain = RetVal.getValue(1);
     }
 
@@ -2251,11 +2244,10 @@ X86TargetLowering::LowerFastCallCCArguments(SDOperand Op, SelectionDAG &DAG) {
       SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
       if (ObjectVT == MVT::i64 && ObjIntRegs) {
         SDOperand ArgValue2 = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
-                                          DAG.getSrcValue(NULL));
+                                          NULL, 0);
         ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
       } else
-        ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
-                               DAG.getSrcValue(NULL));
+        ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
       ArgOffset += ArgIncrement;   // Move on to the next argument.
     }
 
@@ -2329,7 +2321,7 @@ LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
     if (!isFrameAddress)
       // Just load the return address
       Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI,
-                           DAG.getSrcValue(NULL));
+                           NULL, 0);
     else
       Result = DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
                            DAG.getConstant(4, getPointerTy()));
@@ -3051,7 +3043,7 @@ static bool ShouldXformToMOVHLPS(SDNode *Mask) {
 static inline bool isScalarLoadToVector(SDNode *N) {
   if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
     N = N->getOperand(0).Val;
-    return (N->getOpcode() == ISD::LOAD);
+    return ISD::isNON_EXTLoad(N);
   }
   return false;
 }
@@ -3062,7 +3054,7 @@ static inline bool isScalarLoadToVector(SDNode *N) {
 /// half of V2 (and in order). And since V1 will become the source of the
 /// MOVLP, it must be either a vector load or a scalar load to vector.
 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *Mask) {
-  if (V1->getOpcode() != ISD::LOAD && !isScalarLoadToVector(V1))
+  if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
     return false;
 
   unsigned NumElems = Mask->getNumOperands();
@@ -3809,10 +3801,11 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
       // Use two pinsrw instructions to insert a 32 bit value.
       Idx <<= 1;
       if (MVT::isFloatingPoint(N1.getValueType())) {
-        if (N1.getOpcode() == ISD::LOAD) {
+        if (ISD::isNON_EXTLoad(N1.Val)) {
           // Just load directly from f32mem to GR32.
-          N1 = DAG.getLoad(MVT::i32, N1.getOperand(0), N1.getOperand(1),
-                           N1.getOperand(2));
+          LoadSDNode *LD = cast<LoadSDNode>(N1);
+          N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(),
+                           LD->getSrcValue(), LD->getSrcValueOffset());
         } else {
           N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
           N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
@@ -3883,14 +3876,11 @@ X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
     // not the GV offset field.
     if (getTargetMachine().getRelocationModel() != Reloc::Static &&
         DarwinGVRequiresExtraLoad(GV))
-      Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(),
-                           Result, DAG.getSrcValue(NULL));
+      Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
   } else if (Subtarget->isTargetCygwin() || Subtarget->isTargetWindows()) {
-    // FIXME: What's about PIC?
-    if (WindowsGVRequiresExtraLoad(GV)) {
-      Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(),
-                           Result, DAG.getSrcValue(NULL));      
-    }    
+    // FIXME: What about PIC?
+    if (WindowsGVRequiresExtraLoad(GV))
+      Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
   }
   
 
@@ -4028,8 +4018,7 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
     Ops.push_back(DAG.getValueType(Op.getValueType()));
     Ops.push_back(InFlag);
     Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
-    Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
-                         DAG.getSrcValue(NULL));
+    Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
   }
 
   return Result;
@@ -4079,8 +4068,7 @@ SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
   SDOperand FIST = DAG.getNode(Opc, MVT::Other, &Ops[0], Ops.size());
 
   // Load the result.
-  return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
-                     DAG.getSrcValue(NULL));
+  return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
 }
 
 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
@@ -4364,7 +4352,7 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
         SDOperand Chain = Op.getOperand(0);
         SDOperand Value = Op.getOperand(1);
 
-        if (Value.getOpcode() == ISD::LOAD &&
+        if (ISD::isNON_EXTLoad(Value.Val) &&
             (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
           Chain  = Value.getOperand(0);
           MemLoc = Value.getOperand(1);
@@ -4708,7 +4696,7 @@ SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
       Value = DAG.getLoad(MVT::i32, Chain,
                           DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
                                       DAG.getConstant(Offset, SrcVT)),
-                          DAG.getSrcValue(NULL));
+                          NULL, 0);
       Chain = Value.getValue(1);
       Chain = DAG.getStore(Chain, Value,
                            DAG.getNode(ISD::ADD, DstVT, DstAddr,
@@ -4721,7 +4709,7 @@ SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
       Value = DAG.getLoad(MVT::i16, Chain,
                           DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
                                       DAG.getConstant(Offset, SrcVT)),
-                          DAG.getSrcValue(NULL));
+                          NULL, 0);
       Chain = Value.getValue(1);
       Chain = DAG.getStore(Chain, Value,
                            DAG.getNode(ISD::ADD, DstVT, DstAddr,
@@ -4735,7 +4723,7 @@ SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
       Value = DAG.getLoad(MVT::i8, Chain,
                           DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
                                       DAG.getConstant(Offset, SrcVT)),
-                          DAG.getSrcValue(NULL));
+                          NULL, 0);
       Chain = Value.getValue(1);
       Chain = DAG.getStore(Chain, Value,
                            DAG.getNode(ISD::ADD, DstVT, DstAddr,
@@ -5328,7 +5316,7 @@ static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
     } else {
       SDOperand Arg =
         getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
-      if (!Arg.Val || Arg.getOpcode() != ISD::LOAD)
+      if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
         return SDOperand();
       if (!Base)
         Base = Arg.Val;
@@ -5339,10 +5327,11 @@ static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
   }
 
   bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
-  if (isAlign16)
-    return DAG.getLoad(VT, Base->getOperand(0), Base->getOperand(1),
-                       Base->getOperand(2));
-  else {
+  if (isAlign16) {
+    LoadSDNode *LD = cast<LoadSDNode>(Base);
+    return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
+                       LD->getSrcValueOffset());
+  } else {
     // Just use movups, it's shorter.
     std::vector<MVT::ValueType> Tys;
     Tys.push_back(MVT::v4f32);
diff --git a/llvm/lib/Target/X86/X86InstrFPStack.td b/llvm/lib/Target/X86/X86InstrFPStack.td
index 3283ed6b479..c5089873b77 100644
--- a/llvm/lib/Target/X86/X86InstrFPStack.td
+++ b/llvm/lib/Target/X86/X86InstrFPStack.td
@@ -66,7 +66,7 @@ def fp64immneg1 : PatLeaf<(f64 fpimm), [{
   return N->isExactlyValue(-1.0);
 }]>;
 
-def extloadf64f32  : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>;
+def extloadf64f32  : PatFrag<(ops node:$ptr), (f64 (extloadf32 node:$ptr))>;
 
 // Some 'special' instructions
 let usesCustomDAGSchedInserter = 1 in {  // Expanded by the scheduler.
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 6798ad85b53..27c84341791 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -297,25 +297,25 @@ def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
 
-def sextloadi16i1  : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i1))>;
-def sextloadi32i1  : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i1))>;
-def sextloadi16i8  : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i8))>;
-def sextloadi32i8  : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i8))>;
-def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i16))>;
-
-def zextloadi8i1   : PatFrag<(ops node:$ptr), (i8  (zextload node:$ptr, i1))>;
-def zextloadi16i1  : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i1))>;
-def zextloadi32i1  : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i1))>;
-def zextloadi16i8  : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i8))>;
-def zextloadi32i8  : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i8))>;
-def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>;
-
-def extloadi8i1    : PatFrag<(ops node:$ptr), (i8  (extload node:$ptr, i1))>;
-def extloadi16i1   : PatFrag<(ops node:$ptr), (i16 (extload node:$ptr, i1))>;
-def extloadi32i1   : PatFrag<(ops node:$ptr), (i32 (extload node:$ptr, i1))>;
-def extloadi16i8   : PatFrag<(ops node:$ptr), (i16 (extload node:$ptr, i8))>;
-def extloadi32i8   : PatFrag<(ops node:$ptr), (i32 (extload node:$ptr, i8))>;
-def extloadi32i16  : PatFrag<(ops node:$ptr), (i32 (extload node:$ptr, i16))>;
+def sextloadi16i1  : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>;
+def sextloadi32i1  : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>;
+def sextloadi16i8  : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
+def sextloadi32i8  : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
+def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
+
+def zextloadi8i1   : PatFrag<(ops node:$ptr), (i8  (zextloadi1 node:$ptr))>;
+def zextloadi16i1  : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
+def zextloadi32i1  : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
+def zextloadi16i8  : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
+def zextloadi32i8  : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
+def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
+
+def extloadi8i1    : PatFrag<(ops node:$ptr), (i8  (extloadi1 node:$ptr))>;
+def extloadi16i1   : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
+def extloadi32i1   : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
+def extloadi16i8   : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
+def extloadi32i8   : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
+def extloadi32i16  : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
 
 //===----------------------------------------------------------------------===//
 // Instruction templates...
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 55f45287619..2e85167a3bb 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -467,7 +467,7 @@ def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
                 Requires<[HasSSE2]>;
 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
                  "cvtss2sd {$src, $dst|$dst, $src}",
-                 [(set FR64:$dst, (extload addr:$src, f32))]>, XS,
+                 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
                 Requires<[HasSSE2]>;
 
 // Match intrinsics which expect XMM operand(s).
diff --git a/llvm/lib/Target/X86/X86InstrX86-64.td b/llvm/lib/Target/X86/X86InstrX86-64.td
index 027eb170bf7..db060e61518 100644
--- a/llvm/lib/Target/X86/X86InstrX86-64.td
+++ b/llvm/lib/Target/X86/X86InstrX86-64.td
@@ -84,20 +84,20 @@ def i64immSExt8  : PatLeaf<(i64 imm), [{
   return (int64_t)N->getValue() == (int8_t)N->getValue();
 }]>;
 
-def sextloadi64i1  : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i1))>;
-def sextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i8))>;
-def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i16))>;
-def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i32))>;
-
-def zextloadi64i1  : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i1))>;
-def zextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i8))>;
-def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i16))>;
-def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i32))>;
-
-def extloadi64i1   : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i1))>;
-def extloadi64i8   : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i8))>;
-def extloadi64i16  : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i16))>;
-def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i32))>;
+def sextloadi64i1  : PatFrag<(ops node:$ptr), (i64 (sextloadi1 node:$ptr))>;
+def sextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
+def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
+def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
+
+def zextloadi64i1  : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
+def zextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
+def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
+def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
+
+def extloadi64i1   : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
+def extloadi64i8   : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
+def extloadi64i16  : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
+def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
 
 //===----------------------------------------------------------------------===//
 // Instruction list...