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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-02-23 18:34:05 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-02-23 18:34:05 +0000 |
| commit | e08f177ea2cf576e5d619db688ea30ea6937f6ef (patch) | |
| tree | cf3be314605d8cc7792b5fd58b5e73a0033fa697 /llvm/lib/Target/X86 | |
| parent | 31793733a0df327add2e4f7b6c4e8aa611e0bbe7 (diff) | |
| download | bcm5719-llvm-e08f177ea2cf576e5d619db688ea30ea6937f6ef.tar.gz bcm5719-llvm-e08f177ea2cf576e5d619db688ea30ea6937f6ef.zip | |
[X86][AVX] concat_vectors(scalar_to_vector(x),scalar_to_vector(x)) --> broadcast(x)
For AVX1, limit this to i32/f32/i64/f64 loading cases only.
llvm-svn: 354730
Diffstat (limited to 'llvm/lib/Target/X86')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 957987fe3f4..1db9f1274d0 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -41961,6 +41961,13 @@ static SDValue combineInsertSubvector(SDNode *N, SelectionDAG &DAG, SubVec.getOpcode() == X86ISD::SUBV_BROADCAST)) return DAG.getNode(SubVec.getOpcode(), dl, OpVT, SubVec.getOperand(0)); + // concat_vectors(scalar_to_vector(x),scalar_to_vector(x)) -> broadcast(x) + if (SubVec == SubVec2 && SubVec.getOpcode() == ISD::SCALAR_TO_VECTOR && + (Subtarget.hasAVX2() || (OpVT.getScalarSizeInBits() >= 32 && + MayFoldLoad(SubVec.getOperand(0)))) && + SubVec.getOperand(0).getValueType() == OpVT.getScalarType()) + return DAG.getNode(X86ISD::VBROADCAST, dl, OpVT, SubVec.getOperand(0)); + // If we're inserting all zeros into the upper half, change this to // an insert into an all zeros vector. We will match this to a move // with implicit upper bit zeroing during isel. |
