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| author | Craig Topper <craig.topper@intel.com> | 2019-05-11 04:00:27 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-05-11 04:00:27 +0000 |
| commit | bdef12df8d6f0cf7ddb0a626cef377cbcd6d8e30 (patch) | |
| tree | 6e9be8a9b5031e682164d6873ad3fdb1f51eb8ac /llvm/lib/Target/X86 | |
| parent | d0124bd7624426e4b7bdcec96759e7fdae20f13e (diff) | |
| download | bcm5719-llvm-bdef12df8d6f0cf7ddb0a626cef377cbcd6d8e30.tar.gz bcm5719-llvm-bdef12df8d6f0cf7ddb0a626cef377cbcd6d8e30.zip | |
[X86] Add a test case for idempotent atomic operations with speculative load hardening. Fix an additional issue found by the test.
This test covers the fix from r360475 as well.
llvm-svn: 360511
Diffstat (limited to 'llvm/lib/Target/X86')
| -rw-r--r-- | llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp index 02f07d88afc..7b043378819 100644 --- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp +++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp @@ -1719,9 +1719,11 @@ void X86SpeculativeLoadHardeningPass::tracePredStateThroughBlocksAndHarden( // If we have at least one (non-frame-index, non-RIP) register operand, // and neither operand is load-dependent, we need to check the load. + // Also handle explicit references to RSP as used by idempotent atomic + // or with 0. unsigned BaseReg = 0, IndexReg = 0; if (!BaseMO.isFI() && BaseMO.getReg() != X86::RIP && - BaseMO.getReg() != X86::NoRegister) + BaseMO.getReg() != X86::RSP && BaseMO.getReg() != X86::NoRegister) BaseReg = BaseMO.getReg(); if (IndexMO.getReg() != X86::NoRegister) IndexReg = IndexMO.getReg(); |
