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| author | Craig Topper <craig.topper@intel.com> | 2019-03-07 21:22:51 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-03-07 21:22:51 +0000 |
| commit | b3af5d3e57107a3bffe4c2d38b22ae96cee52245 (patch) | |
| tree | bcc77d1a4dad0b1279617c73665ae553bee1cd8a /llvm/lib/Target/X86 | |
| parent | 4e467043fbb5fc9c7c426019c40f9db85d84f31f (diff) | |
| download | bcm5719-llvm-b3af5d3e57107a3bffe4c2d38b22ae96cee52245.tar.gz bcm5719-llvm-b3af5d3e57107a3bffe4c2d38b22ae96cee52245.zip | |
[X86] Model ADC/SBB with immediate 0 more accurately in the Haswell scheduler model
Haswell and possibly Sandybridge have an optimization for ADC/SBB with immediate 0 to use a single uop flow. This only applies GR16/GR32/GR64 with an 8-bit immediate. It does not apply to GR8. It also does not apply to the implicit AX/EAX/RAX forms.
Differential Revision: https://reviews.llvm.org/D59058
llvm-svn: 355635
Diffstat (limited to 'llvm/lib/Target/X86')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index dc040e0e7d3..5fc838a2ce3 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -1848,4 +1848,34 @@ def: InstRW<[HWWriteResGroup192], (instrs VGATHERQPSrm, def: InstRW<[WriteZero], (instrs CLC)>; +// The 0x83 ADC/SBB opcodes have special support for immediate 0 to only require +// a single uop. It does not apply to the GR8 encoding. And only applies to the +// 8-bit immediate since using larger immediate for 0 would be silly. +// Unfortunately, this optimization does not apply to the AX/EAX/RAX short +// encodings we convert to in MCInstLowering so we exclude AX/EAX/RAX here since +// we schedule before that point. +// TODO: Should we disable using the short encodings on these CPUs? +def HWFastADC0 : MCSchedPredicate< + CheckAll<[ + CheckImmOperand<2, 0>, // Second MCOperand is Imm and has value 0. + CheckNot<CheckRegOperand<1, AX>>, // First MCOperand is not register AX + CheckNot<CheckRegOperand<1, EAX>>, // First MCOperand is not register EAX + CheckNot<CheckRegOperand<1, RAX>> // First MCOperand is not register RAX + ]> +>; + +def HWWriteADC0 : SchedWriteRes<[HWPort06]> { + let Latency = 1; + let NumMicroOps = 1; + let ResourceCycles = [1]; +} + +def HWWriteADC : SchedWriteVariant<[ + SchedVar<HWFastADC0, [HWWriteADC0]>, + SchedVar<NoSchedPred, [WriteADC]> +]>; + +def : InstRW<[HWWriteADC], (instrs ADC16ri8, ADC32ri8, ADC64ri8, + SBB16ri8, SBB32ri8, SBB64ri8)>; + } // SchedModel |
