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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-09-30 17:57:34 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-09-30 17:57:34 +0000 |
| commit | a8dd6f4f309b55c43a5b263c3aa178fa5bca4b30 (patch) | |
| tree | 57dc43373d9bb3b12d40217a7be071d694475faa /llvm/lib/Target/X86 | |
| parent | 619569841ad69800ee55ef53e13bf07c4c459776 (diff) | |
| download | bcm5719-llvm-a8dd6f4f309b55c43a5b263c3aa178fa5bca4b30.tar.gz bcm5719-llvm-a8dd6f4f309b55c43a5b263c3aa178fa5bca4b30.zip | |
[X86][SSE] Fold (VSRAI (VSHLI X, C1), C1) --> X iff NumSignBits(X) > C1
Remove sign extend in register style pattern if the sign is already extended enough
llvm-svn: 314599
Diffstat (limited to 'llvm/lib/Target/X86')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index b927178265a..2d7cf5c1b98 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -31845,6 +31845,15 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG, N0.getOpcode() == X86ISD::VSRAI) return DAG.getNode(X86ISD::VSRLI, SDLoc(N), VT, N0.getOperand(0), N1); + // fold (VSRAI (VSHLI X, C1), C1) --> X iff NumSignBits(X) > C1 + if (Opcode == X86ISD::VSRAI && N0.getOpcode() == X86ISD::VSHLI && + N1 == N0.getOperand(1)) { + SDValue N00 = N0.getOperand(0); + unsigned NumSignBits = DAG.ComputeNumSignBits(N00); + if (ShiftVal.ult(NumSignBits)) + return N00; + } + // We can decode 'whole byte' logical bit shifts as shuffles. if (LogicalShift && (ShiftVal.getZExtValue() % 8) == 0) { SDValue Op(N, 0); |
