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| author | Craig Topper <craig.topper@intel.com> | 2017-12-31 07:38:33 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-31 07:38:33 +0000 |
| commit | a362dee774a705e0401a7b19e4baf5e95d1a6d07 (patch) | |
| tree | 5b33d5699f16fdfebcc69ecee8ad6b3386f69996 /llvm/lib/Target/X86 | |
| parent | 7ba1b768542023e32f9f470bc3d61d27f54348ee (diff) | |
| download | bcm5719-llvm-a362dee774a705e0401a7b19e4baf5e95d1a6d07.tar.gz bcm5719-llvm-a362dee774a705e0401a7b19e4baf5e95d1a6d07.zip | |
[X86] Remove AND32ri8 from pattern for v1i1 load.
I don't think anything would actually expect the other bits to be zero.
llvm-svn: 321596
Diffstat (limited to 'llvm/lib/Target/X86')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index ebf9bd7d8b0..901efbaf408 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -2748,7 +2748,7 @@ let Predicates = [HasAVX512] in { def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst), (KMOVWmk addr:$dst, VK16:$src)>; def : Pat<(v1i1 (load addr:$src)), - (COPY_TO_REGCLASS (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), VK1)>; + (COPY_TO_REGCLASS (MOVZX32rm8 addr:$src), VK1)>; def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))), (KMOVWkm addr:$src)>; } |
