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authorCraig Topper <craig.topper@intel.com>2018-01-06 06:08:04 +0000
committerCraig Topper <craig.topper@intel.com>2018-01-06 06:08:04 +0000
commit8c2ea74e74752399d00a84fcfe831e1e312088dd (patch)
treef28d1dcf599c51199595c1d363b452301c353c99 /llvm/lib/Target/X86
parentaf1d257571f29bbfebf64fe5314bb41475191aad (diff)
downloadbcm5719-llvm-8c2ea74e74752399d00a84fcfe831e1e312088dd.tar.gz
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[X86] Call lowerShuffleAsRepeatedMaskAndLanePermute from lowerV4I64VectorShuffle.
llvm-svn: 321929
Diffstat (limited to 'llvm/lib/Target/X86')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp6
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c518b354471..dab97501b85 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -13309,6 +13309,12 @@ static SDValue lowerV4I64VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask,
lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
return V;
+ // Try to create an in-lane repeating shuffle mask and then shuffle the
+ // the results into the target lanes.
+ if (SDValue V = lowerShuffleAsRepeatedMaskAndLanePermute(
+ DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
+ return V;
+
// Try to simplify this by merging 128-bit lanes to enable a lane-based
// shuffle. However, if we have AVX2 and either inputs are already in place,
// we will be able to shuffle even across lanes the other input in a single
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