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author | Sanjay Patel <spatel@rotateright.com> | 2019-03-14 15:32:34 +0000 |
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committer | Sanjay Patel <spatel@rotateright.com> | 2019-03-14 15:32:34 +0000 |
commit | 5d1df114e8777d2cec59d26152c1adc3ddbcafcd (patch) | |
tree | 301a2aa35e4fc887445b939a4e7631ad2e4f397a /llvm/lib/Target/X86 | |
parent | 4b1a5099240d25d3a59ea4834e20bc7b56b62032 (diff) | |
download | bcm5719-llvm-5d1df114e8777d2cec59d26152c1adc3ddbcafcd.tar.gz bcm5719-llvm-5d1df114e8777d2cec59d26152c1adc3ddbcafcd.zip |
[x86] prevent infinite looping from vselect commutation (PR41066)
This is an immediate fix for:
https://bugs.llvm.org/show_bug.cgi?id=41066
...but as noted there and the code comments, we should do better
by stubbing this out sooner.
llvm-svn: 356158
Diffstat (limited to 'llvm/lib/Target/X86')
-rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index ef6622e41aa..47ebe254b99 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -34559,11 +34559,15 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG, assert(CondVT.isVector() && "Vector select expects a vector selector!"); - bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode()); // Check if the first operand is all zeros and Cond type is vXi1. // This situation only applies to avx512. - if (TValIsAllZeros && Subtarget.hasAVX512() && Cond.hasOneUse() && - CondVT.getVectorElementType() == MVT::i1) { + // TODO: Use isNullOrNullSplat() to distinguish constants with undefs? + // TODO: Can we assert that both operands are not zeros (because that should + // get simplified at node creation time)? + bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode()); + bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode()); + if (TValIsAllZeros && !FValIsAllZeros && Subtarget.hasAVX512() && + Cond.hasOneUse() && CondVT.getVectorElementType() == MVT::i1) { // Invert the cond to not(cond) : xor(op,allones)=not(op) SDValue CondNew = DAG.getNOT(DL, Cond, CondVT); // Vselect cond, op1, op2 = Vselect not(cond), op2, op1 @@ -34578,11 +34582,9 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG, if (CondVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) return SDValue(); - bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode()); - bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode()); - // Try to invert the condition if true value is not all 1s and false value is // not all 0s. Only do this if the condition has one use. + bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode()); if (!TValIsAllOnes && !FValIsAllZeros && Cond.hasOneUse() && // Check if the selector will be produced by CMPP*/PCMP*. Cond.getOpcode() == ISD::SETCC && |