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authorNate Begeman <natebegeman@mac.com>2006-01-14 03:14:10 +0000
committerNate Begeman <natebegeman@mac.com>2006-01-14 03:14:10 +0000
commit2fba8a3aaa778176a68dfc78b39bcb1b4932a0b9 (patch)
tree0287e4215ca009958855fc3a55b9ce3d6d2c2dc6 /llvm/lib/Target/X86
parent8f8504b3c61a6a651ceda2eae60f815b4d625fdf (diff)
downloadbcm5719-llvm-2fba8a3aaa778176a68dfc78b39bcb1b4932a0b9.tar.gz
bcm5719-llvm-2fba8a3aaa778176a68dfc78b39bcb1b4932a0b9.zip
bswap implementation
llvm-svn: 25312
Diffstat (limited to 'llvm/lib/Target/X86')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp2
-rw-r--r--llvm/lib/Target/X86/X86InstrInfo.td4
2 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d93ec3a5375..a749380b864 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -109,6 +109,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
if (!X86DAGIsel) {
+ setOperationAction(ISD::BSWAP , MVT::i32 , Expand);
setOperationAction(ISD::ROTL , MVT::i8 , Expand);
setOperationAction(ISD::ROTR , MVT::i8 , Expand);
setOperationAction(ISD::ROTL , MVT::i16 , Expand);
@@ -116,6 +117,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::ROTL , MVT::i32 , Expand);
setOperationAction(ISD::ROTR , MVT::i32 , Expand);
}
+ setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
setOperationAction(ISD::READIO , MVT::i1 , Expand);
setOperationAction(ISD::READIO , MVT::i8 , Expand);
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 291abd48e35..5427e249d0f 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -518,7 +518,9 @@ def POP32r : I<0x58, AddRegFrm,
let isTwoAddress = 1 in // R32 = bswap R32
def BSWAP32r : I<0xC8, AddRegFrm,
- (ops R32:$dst, R32:$src), "bswap{l} $dst", []>, TB;
+ (ops R32:$dst, R32:$src),
+ "bswap{l} $dst",
+ [(set R32:$dst, (bswap R32:$src))]>, TB;
def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8
(ops R8:$src1, R8:$src2),
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