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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-10-24 18:44:12 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-10-24 18:44:12 +0000 |
| commit | ac840058416d72a3c62eedc81ba65b634a201c5b (patch) | |
| tree | 1490dab8254ebed3aa7ba561afaf50dd802cbac9 /llvm/lib/Target/X86/X86TargetTransformInfo.cpp | |
| parent | 6b6d9bbd48c1079b06404059eb2ea37b913b0d27 (diff) | |
| download | bcm5719-llvm-ac840058416d72a3c62eedc81ba65b634a201c5b.tar.gz bcm5719-llvm-ac840058416d72a3c62eedc81ba65b634a201c5b.zip | |
[CostModel][X86] Add vXi8 vector division by constants costs.
ISD::MULHS/ISD::MULHU lowering of vXi8 types means we expand these in TargetLowering BuildSDIV/BuildUDIV.
llvm-svn: 345175
Diffstat (limited to 'llvm/lib/Target/X86/X86TargetTransformInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 29306d75454..b77ac5c9953 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -346,6 +346,10 @@ int X86TTIImpl::getArithmeticInstrCost( } static const CostTblEntry AVX512BWConstCostTable[] = { + { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence + { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence + { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence + { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence @@ -376,6 +380,10 @@ int X86TTIImpl::getArithmeticInstrCost( } static const CostTblEntry AVX2ConstCostTable[] = { + { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence + { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence + { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence + { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence @@ -394,6 +402,14 @@ int X86TTIImpl::getArithmeticInstrCost( } static const CostTblEntry SSE2ConstCostTable[] = { + { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. + { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. + { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence + { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence + { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. + { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. + { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence + { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence |
