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authorEvan Cheng <evan.cheng@apple.com>2009-01-03 04:24:44 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-01-03 04:24:44 +0000
commit6e100a62b1095ffb0f64756e4f697ff371856a36 (patch)
tree070b967a8d337f3e50d4ba0724c82b3c837c6651 /llvm/lib/Target/X86/X86Subtarget.cpp
parent9a3ec1b208e60426fe289cedf8d22b47247b7937 (diff)
downloadbcm5719-llvm-6e100a62b1095ffb0f64756e4f697ff371856a36.tar.gz
bcm5719-llvm-6e100a62b1095ffb0f64756e4f697ff371856a36.zip
Add Intel processors core i7 and atom.
llvm-svn: 61603
Diffstat (limited to 'llvm/lib/Target/X86/X86Subtarget.cpp')
-rw-r--r--llvm/lib/Target/X86/X86Subtarget.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp
index a7df68b19f8..c6cda56f7dd 100644
--- a/llvm/lib/Target/X86/X86Subtarget.cpp
+++ b/llvm/lib/Target/X86/X86Subtarget.cpp
@@ -204,6 +204,7 @@ static const char *GetCurrentX86CPU() {
unsigned Family = 0;
unsigned Model = 0;
DetectFamilyModel(EAX, Family, Model);
+ bool HasSSE42 = (ECX >> 19) & 0x1;
X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
bool Em64T = (EDX >> 29) & 0x1;
@@ -254,7 +255,7 @@ static const char *GetCurrentX86CPU() {
case 28:
// Intel Atom, and Core i7 both have this model.
// Atom has SSSE3, Core i7 has SSE4.2
- return "core2";
+ return (HasSSE42) ? "corei7" : "atom";
default:
return (Em64T) ? "x86-64" : "pentium4";
}
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