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author | Craig Topper <craig.topper@intel.com> | 2019-05-15 04:15:46 +0000 |
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committer | Craig Topper <craig.topper@intel.com> | 2019-05-15 04:15:46 +0000 |
commit | 384d46c0d5be4cece38d8f7448ff80e49c1ce3b8 (patch) | |
tree | 7d862c460e54cabc2f449d1d17ee0c5864e9c18a /llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp | |
parent | a23cc727d8155d390a04f4ccf989eda561c9fc06 (diff) | |
download | bcm5719-llvm-384d46c0d5be4cece38d8f7448ff80e49c1ce3b8.tar.gz bcm5719-llvm-384d46c0d5be4cece38d8f7448ff80e49c1ce3b8.zip |
[X86] Use OR32mi8Locked instead of LOCK_OR32mi8 in emitLockedStackOp.
They encode the same way, but OR32mi8Locked sets hasUnmodeledSideEffects set
which should be stronger than the mayLoad/mayStore on LOCK_OR32mi8. I think
this makes sense since we are using it as a fence.
This also seems to hide the operation from the speculative load hardening pass
so I've reverted r360511.
llvm-svn: 360747
Diffstat (limited to 'llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp')
-rw-r--r-- | llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp index 7b043378819..02f07d88afc 100644 --- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp +++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp @@ -1719,11 +1719,9 @@ void X86SpeculativeLoadHardeningPass::tracePredStateThroughBlocksAndHarden( // If we have at least one (non-frame-index, non-RIP) register operand, // and neither operand is load-dependent, we need to check the load. - // Also handle explicit references to RSP as used by idempotent atomic - // or with 0. unsigned BaseReg = 0, IndexReg = 0; if (!BaseMO.isFI() && BaseMO.getReg() != X86::RIP && - BaseMO.getReg() != X86::RSP && BaseMO.getReg() != X86::NoRegister) + BaseMO.getReg() != X86::NoRegister) BaseReg = BaseMO.getReg(); if (IndexMO.getReg() != X86::NoRegister) IndexReg = IndexMO.getReg(); |