[X86] Use OR32mi8Locked instead of LOCK_OR32mi8 in emitLockedStackOp.

They encode the same way, but OR32mi8Locked sets hasUnmodeledSideEffects set
which should be stronger than the mayLoad/mayStore on LOCK_OR32mi8. I think
this makes sense since we are using it as a fence.

This also seems to hide the operation from the speculative load hardening pass
so I've reverted r360511.

llvm-svn: 360747

2 files changed, 3 insertions, 5 deletions

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e3b97162020..c2cc3f33de0 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -25872,7 +25872,7 @@ static SDValue emitLockedStackOp(SelectionDAG &DAG,
       DAG.getRegister(0, MVT::i16),                         // Segment.
       Zero,
       Chain};
-    SDNode *Res = DAG.getMachineNode(X86::LOCK_OR32mi8, DL, MVT::i32,
+    SDNode *Res = DAG.getMachineNode(X86::OR32mi8Locked, DL, MVT::i32,
                                      MVT::Other, Ops);
     return SDValue(Res, 1);
   }
@@ -25887,7 +25887,7 @@ static SDValue emitLockedStackOp(SelectionDAG &DAG,
     Zero,
     Chain
   };
-  SDNode *Res = DAG.getMachineNode(X86::LOCK_OR32mi8, DL, MVT::i32,
+  SDNode *Res = DAG.getMachineNode(X86::OR32mi8Locked, DL, MVT::i32,
                                    MVT::Other, Ops);
   return SDValue(Res, 1);
 }
diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
index 7b043378819..02f07d88afc 100644
--- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
+++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
@@ -1719,11 +1719,9 @@ void X86SpeculativeLoadHardeningPass::tracePredStateThroughBlocksAndHarden(
 
         // If we have at least one (non-frame-index, non-RIP) register operand,
         // and neither operand is load-dependent, we need to check the load.
-        // Also handle explicit references to RSP as used by idempotent atomic
-        // or with 0.
         unsigned BaseReg = 0, IndexReg = 0;
         if (!BaseMO.isFI() && BaseMO.getReg() != X86::RIP &&
-            BaseMO.getReg() != X86::RSP && BaseMO.getReg() != X86::NoRegister)
+            BaseMO.getReg() != X86::NoRegister)
           BaseReg = BaseMO.getReg();
         if (IndexMO.getReg() != X86::NoRegister)
           IndexReg = IndexMO.getReg();