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| author | Igor Breger <igor.breger@intel.com> | 2017-03-23 12:13:29 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2017-03-23 12:13:29 +0000 |
| commit | 8a924bea78f706d517b0b20b458b12a6eccfce1d (patch) | |
| tree | 8a4ba10160d2ce7c230c95f55963ab8ed91a5e16 /llvm/lib/Target/X86/X86RegisterBankInfo.cpp | |
| parent | f9371395300cc20d7a302e647de9ecda4bdf6b7e (diff) | |
| download | bcm5719-llvm-8a924bea78f706d517b0b20b458b12a6eccfce1d.tar.gz bcm5719-llvm-8a924bea78f706d517b0b20b458b12a6eccfce1d.zip | |
[GlobalISel][X86] clang-format. NFC
llvm-svn: 298590
Diffstat (limited to 'llvm/lib/Target/X86/X86RegisterBankInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterBankInfo.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp index fd9f62480c5..c06e4baa3b7 100644 --- a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp @@ -72,8 +72,7 @@ X86RegisterBankInfo::getOperandsMapping(const MachineInstr &MI, bool isFP) { unsigned NumOperands = MI.getNumOperands(); LLT Ty = MRI.getType(MI.getOperand(0).getReg()); - if (NumOperands != 3 || - (Ty != MRI.getType(MI.getOperand(1).getReg())) || + if (NumOperands != 3 || (Ty != MRI.getType(MI.getOperand(1).getReg())) || (Ty != MRI.getType(MI.getOperand(2).getReg()))) llvm_unreachable("Unsupported operand maping yet."); @@ -106,7 +105,7 @@ X86RegisterBankInfo::getOperandsMapping(const MachineInstr &MI, bool isFP) { ValMapIdx = VMI_3OpsFp64Idx; break; default: - llvm_unreachable("Unsupported register size."); + llvm_unreachable("Unsupported register size."); } } } else { |
