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| author | Craig Topper <craig.topper@intel.com> | 2017-09-27 20:34:17 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-09-27 20:34:17 +0000 |
| commit | c16a47296606d41a5fb432ae1c978fd77ac9f511 (patch) | |
| tree | 29f210f25fed6c0d4b760541961670742afc162e /llvm/lib/Target/X86/X86MCInstLower.cpp | |
| parent | e0d829009459722105826bb9b678334d9ba337b3 (diff) | |
| download | bcm5719-llvm-c16a47296606d41a5fb432ae1c978fd77ac9f511.tar.gz bcm5719-llvm-c16a47296606d41a5fb432ae1c978fd77ac9f511.zip | |
Revert r314249 "Recommit r314151 "[X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like the NOREX version of TEST."""
This caused PR34751
llvm-svn: 314339
Diffstat (limited to 'llvm/lib/Target/X86/X86MCInstLower.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86MCInstLower.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index 7a770d6cbc5..36d81128acf 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -604,7 +604,9 @@ ReSimplify: // Note, we are currently not handling the following instructions: // MOV64ao8, MOV64o8a // XCHG16ar, XCHG32ar, XCHG64ar + case X86::MOV8mr_NOREX: case X86::MOV8mr: + case X86::MOV8rm_NOREX: case X86::MOV8rm: case X86::MOV16mr: case X86::MOV16rm: @@ -613,7 +615,9 @@ ReSimplify: unsigned NewOpc; switch (OutMI.getOpcode()) { default: llvm_unreachable("Invalid opcode"); + case X86::MOV8mr_NOREX: case X86::MOV8mr: NewOpc = X86::MOV8o32a; break; + case X86::MOV8rm_NOREX: case X86::MOV8rm: NewOpc = X86::MOV8ao32; break; case X86::MOV16mr: NewOpc = X86::MOV16o32a; break; case X86::MOV16rm: NewOpc = X86::MOV16ao32; break; |
