From c16a47296606d41a5fb432ae1c978fd77ac9f511 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 27 Sep 2017 20:34:17 +0000 Subject: Revert r314249 "Recommit r314151 "[X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like the NOREX version of TEST.""" This caused PR34751 llvm-svn: 314339 --- llvm/lib/Target/X86/X86MCInstLower.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'llvm/lib/Target/X86/X86MCInstLower.cpp') diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index 7a770d6cbc5..36d81128acf 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -604,7 +604,9 @@ ReSimplify: // Note, we are currently not handling the following instructions: // MOV64ao8, MOV64o8a // XCHG16ar, XCHG32ar, XCHG64ar + case X86::MOV8mr_NOREX: case X86::MOV8mr: + case X86::MOV8rm_NOREX: case X86::MOV8rm: case X86::MOV16mr: case X86::MOV16rm: @@ -613,7 +615,9 @@ ReSimplify: unsigned NewOpc; switch (OutMI.getOpcode()) { default: llvm_unreachable("Invalid opcode"); + case X86::MOV8mr_NOREX: case X86::MOV8mr: NewOpc = X86::MOV8o32a; break; + case X86::MOV8rm_NOREX: case X86::MOV8rm: NewOpc = X86::MOV8ao32; break; case X86::MOV16mr: NewOpc = X86::MOV16o32a; break; case X86::MOV16rm: NewOpc = X86::MOV16ao32; break; -- cgit v1.2.3