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| author | Chris Lattner <sabre@nondot.org> | 2010-02-11 08:45:56 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-02-11 08:45:56 +0000 |
| commit | fbf1f02fee7c99f7e932852c89f3f871c8cdf4c7 (patch) | |
| tree | 417f403a66009bfbf443d010a2889aedd15f3f42 /llvm/lib/Target/X86/X86MCCodeEmitter.cpp | |
| parent | 5a4ec879bfe6116dceed6b7782496b37a71571b7 (diff) | |
| download | bcm5719-llvm-fbf1f02fee7c99f7e932852c89f3f871c8cdf4c7.tar.gz bcm5719-llvm-fbf1f02fee7c99f7e932852c89f3f871c8cdf4c7.zip | |
dont' call getX86RegNum on X86::RIP, it doesn't like that. This
fixes the remaining x86-64 jit failures afaik.
llvm-svn: 95867
Diffstat (limited to 'llvm/lib/Target/X86/X86MCCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86MCCodeEmitter.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/X86MCCodeEmitter.cpp index ef1733f9939..ba1bdc7851d 100644 --- a/llvm/lib/Target/X86/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/X86MCCodeEmitter.cpp @@ -175,8 +175,10 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, const MCOperand &Scale = MI.getOperand(Op+1); const MCOperand &IndexReg = MI.getOperand(Op+2); unsigned BaseReg = Base.getReg(); - unsigned BaseRegNo = BaseReg != 0 ? GetX86RegNum(Base) : -1U; - + unsigned BaseRegNo = -1U; + if (BaseReg != 0 && BaseReg != X86::RIP) + BaseRegNo = GetX86RegNum(Base); + // Determine whether a SIB byte is needed. // If no BaseReg, issue a RIP relative instruction only if the MCE can // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table |
