change getSizeOfImm and getBaseOpcodeFor to just take

TSFlags directly instead of a TargetInstrDesc.

llvm-svn: 95405

1 files changed, 13 insertions, 5 deletions

diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 9dccfbdff57..affb5a0c5d8 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -640,11 +640,11 @@ public:
   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
   // specified machine instruction.
   //
-  static unsigned char getBaseOpcodeFor(const TargetInstrDesc &TID) {
-    return TID.TSFlags >> X86II::OpcodeShift;
+  static unsigned char getBaseOpcodeFor(unsigned TSFlags) {
+    return TSFlags >> X86II::OpcodeShift;
   }
-  unsigned char getBaseOpcodeFor(unsigned Opcode) const {
-    return getBaseOpcodeFor(get(Opcode));
+  unsigned char getBaseOpcodeForOpcode(unsigned Opcode) const {
+    return getBaseOpcodeFor(get(Opcode).TSFlags);
   }
   
   static bool isX86_64NonExtLowByteReg(unsigned reg) {
@@ -652,7 +652,15 @@ public:
           reg == X86::SIL || reg == X86::DIL);
   }
   
-  static unsigned sizeOfImm(const TargetInstrDesc *Desc);
+  static unsigned getSizeOfImm(unsigned TSFlags) {
+    switch (TSFlags & X86II::ImmMask) {
+    default: assert(0 && "Unknown immediate size");
+    case X86II::Imm8:   return 1;
+    case X86II::Imm16:  return 2;
+    case X86II::Imm32:  return 4;
+    case X86II::Imm64:  return 8;
+    }
+  }    
   static bool isX86_64ExtendedReg(const MachineOperand &MO);
   static unsigned determineREX(const MachineInstr &MI);