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authorEvan Cheng <evan.cheng@apple.com>2010-01-13 00:30:23 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-01-13 00:30:23 +0000
commit30bebff456934bec78391fc220846dc63fb3fbe9 (patch)
tree26fca2d93e82e49a5d563b3181392685de647fdb /llvm/lib/Target/X86/X86InstrInfo.h
parente1ac8d17422098756cb7ce62be6552096ebf9b34 (diff)
downloadbcm5719-llvm-30bebff456934bec78391fc220846dc63fb3fbe9.tar.gz
bcm5719-llvm-30bebff456934bec78391fc220846dc63fb3fbe9.zip
Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg.
For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used. llvm-svn: 93278
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrInfo.h')
-rw-r--r--llvm/lib/Target/X86/X86InstrInfo.h16
1 files changed, 9 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 6ae7808e2dd..0ab85f4f45b 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -448,13 +448,15 @@ public:
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
- /// isCoalescableInstr - Return true if the instruction is "coalescable". That
- /// is, it's like a copy where it's legal for the source to overlap the
- /// destination. e.g. X86::MOVSX64rr32.
- virtual bool isCoalescableInstr(const MachineInstr &MI, bool &isCopy,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
-
+ /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
+ /// extension instruction. That is, it's like a copy where it's legal for the
+ /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
+ /// true, then it's expected the pre-extension value is available as a subreg
+ /// of the result register. This also returns the sub-register index in
+ /// SubIdx.
+ virtual bool isCoalescableExtInstr(const MachineInstr &MI,
+ unsigned &SrcReg, unsigned &DstReg,
+ unsigned &SubIdx) const;
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
/// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
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