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| author | Craig Topper <craig.topper@gmail.com> | 2012-12-29 18:18:20 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-12-29 18:18:20 +0000 |
| commit | fe82eb6bcd973fe4c6ea68ba661cb56715b42358 (patch) | |
| tree | 2f0b8e85601f1a4420e824991249d92e9ca47cae /llvm/lib/Target/X86/X86InstrInfo.cpp | |
| parent | a96d74585fb576c80d6c8cc05b3ee453242e4045 (diff) | |
| download | bcm5719-llvm-fe82eb6bcd973fe4c6ea68ba661cb56715b42358.tar.gz bcm5719-llvm-fe82eb6bcd973fe4c6ea68ba661cb56715b42358.zip | |
Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those.
llvm-svn: 171237
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index f3ec067bdb3..a7424096a8c 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -467,9 +467,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 }, - { X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 }, { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 }, - { X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 }, { X86::SQRTSDr, X86::SQRTSDm, 0 }, { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, { X86::SQRTSSr, X86::SQRTSSm, 0 }, @@ -528,9 +526,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 }, { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 }, { X86::VSQRTPDr, X86::VSQRTPDm, 0 }, - { X86::VSQRTPDr_Int, X86::VSQRTPDm_Int, 0 }, { X86::VSQRTPSr, X86::VSQRTPSm, 0 }, - { X86::VSQRTPSr_Int, X86::VSQRTPSm_Int, 0 }, { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 }, { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }, { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE }, @@ -554,11 +550,8 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) { X86::VRCPPSYr, X86::VRCPPSYm, 0 }, { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 }, { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 }, - { X86::VRSQRTPSYr_Int, X86::VRSQRTPSYm_Int, 0 }, { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 }, - { X86::VSQRTPDYr_Int, X86::VSQRTPDYm_Int, 0 }, { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 }, - { X86::VSQRTPSYr_Int, X86::VSQRTPSYm_Int, 0 }, { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE }, { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE }, @@ -4670,13 +4663,9 @@ bool X86InstrInfo::isHighLatencyDef(int opc) const { case X86::DIVSSrr: case X86::DIVSSrr_Int: case X86::SQRTPDm: - case X86::SQRTPDm_Int: case X86::SQRTPDr: - case X86::SQRTPDr_Int: case X86::SQRTPSm: - case X86::SQRTPSm_Int: case X86::SQRTPSr: - case X86::SQRTPSr_Int: case X86::SQRTSDm: case X86::SQRTSDm_Int: case X86::SQRTSDr: @@ -4695,13 +4684,9 @@ bool X86InstrInfo::isHighLatencyDef(int opc) const { case X86::VDIVSSrr: case X86::VDIVSSrr_Int: case X86::VSQRTPDm: - case X86::VSQRTPDm_Int: case X86::VSQRTPDr: - case X86::VSQRTPDr_Int: case X86::VSQRTPSm: - case X86::VSQRTPSm_Int: case X86::VSQRTPSr: - case X86::VSQRTPSr_Int: case X86::VSQRTSDm: case X86::VSQRTSDm_Int: case X86::VSQRTSDr: |
